From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33C16C54ED1 for ; Fri, 23 May 2025 17:23:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=F8I6jN7fPcw06UYByKUEADXyNWwQhc00Srn0zHebIPw=; b=DiZfXThmSRTShZO/mcq0ZdrMz/ cGNWM/LwtPmWxcaIqokMzV+34r7nfZ5jpQte1ZI/EXgsp8h55KUDl3JgU9MTGaE/oYizxo+lvPmiF 2wWhQWwTw7TEGFzsUM6M34pOZzYlmPN2K+FHw9bsVJT5gkGRfHtAMuCDxgjKILX0q1OuBt06uvGJ+ wtG27Zvug+B22GUZGtST1oYfCvx09DRgMSA8BHYbWg+kfMCmKl9rV6pkogEB03nIpLVL1Z+k6iWz3 k0dInr1OkOinoAHJFMVxZRjxMSMZK/HlSwex4L+ECryP5RvJwF0rkzpKcvqegCNLo3CR5HECvKR7Z e70xaqLg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uIW7W-00000004WwH-0QEj; Fri, 23 May 2025 17:23:46 +0000 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uIVyn-00000004VTT-29IQ for linux-riscv@lists.infradead.org; Fri, 23 May 2025 17:14:47 +0000 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-231f5a7baa2so995475ad.0 for ; Fri, 23 May 2025 10:14:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1748020484; x=1748625284; darn=lists.infradead.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=+ILKfp+PhHp1JJ4V01gttad8fE6fV6QpycD/TPbbAGI=; b=IIb+5RVyyBVZmq2Crccj8e4tY0xA2MNLEeQmBmJXJh5th0KY+nPisVBuhuCHEdi+af IhTQnnC1JU/n451WAdB2lVoAnLVjrvbd0rcXwNS8XSipAwCFCCVEB8GDBqQ3pwsz65KE kQxTyVzO85DPztfR4GbYiTvLLfOaBUQYeiGULzIUHwLU7zQ86/k31N/wZv3Y304YZXgC e2OoUwQo/tNuNx0N7ZxkjohJxbiVU7NbpKKtPC2ue79zAfPllOXwu72s8WcBBQTvKenO XPvX2RDU0ujiPBkpbaJXxbjcbr7a3tmWMKXjj0nt4/mestiOuA+n6tf79vA0cpYD933B wpLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748020484; x=1748625284; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=+ILKfp+PhHp1JJ4V01gttad8fE6fV6QpycD/TPbbAGI=; b=Xvwzwb3P9A8j41nIY+IHw0IKunFsgNR4kD6rCU2vca7F+9L3ueW1fKr8u7Yi8Pyz4j fqFSkDPoLat09nIWnqoo7eZeexfsjcxYSDKxc6Lf1dA7EvbFRj066QnGqJ+jrIMN5CwP dxV+fZaGa2DxumojAQaztaqD3RLn9tqXy9cxt9wxJfuh7kAg1K7pKa5gu81HGTxDvLj2 PPRxG4a4prUh3745EwckLsC6oiibN2+XkDp+5BhqZnw0K4tyf8AB7+4zHqsxbgOFCr7n 9vz6cw5W/MmfoyE6o/7uGvNboI+sMDQzmipOV0jVBEoiEYJxkVbglFfJPFKjEUAYN86G 8mag== X-Forwarded-Encrypted: i=1; AJvYcCWLCAgQHO1oCP7KHOJWW+4DxmCgtByy097uIiJ3lYdlvGoNBOJv8QRuyJAep0apflIKFgzVjBjqQ59Zvg==@lists.infradead.org X-Gm-Message-State: AOJu0YySAaHi7cQuhB3I/X3yER6JjaFofBbTXk6vbOvX2kYwsAGXiCvj PAAbih3xZ6PId6hp/by66wAWbjbWL6oaN2dZi98fuf9ft/7svSfsJVBX2fOy9vRdPx8= X-Gm-Gg: ASbGncunfu6GFD7lV/H0B4Nr1tlvvdf2ipkCHr8fso//daH7JQ4iTx8Xnvl2GM1D9xS p04Td8ucQp5eh6WCEpPK+s0Uuxi/eGBbgIby/YYQypQhXCkXt3O2GrvZOe5q+Hj9lKs/Q2pJZbJ Z7xZ6cnQRmsX0TwLOxpfbC04flf4CD02o6WLSqbTJYKVK1x8/liVakZqNV32N5zooEF/WtOcwdD a1dNRkSTYkuaPUkyibXcWRz0avAGGvssaJMAJhQiOgvd0MDQ6DePzp7wdTaKOtoykPdjaIJSrM1 UKMB17qY28atgZc934jngkZ4atJZ8tnq2fQIl/viACIknv+1b8iZ57xOB4RGqQ== X-Google-Smtp-Source: AGHT+IFYZp9eIXDMvWYA6hNO9vlZGOyZj5S0G8khsz4GfqLECIT4FzVceMBBxmyKMIqEgFnPJUUCxQ== X-Received: by 2002:a17:902:ea04:b0:233:fbb3:c5bc with SMTP id d9443c01a7336-23414f6d173mr2700345ad.19.1748020484256; Fri, 23 May 2025 10:14:44 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4ac91acsm126024045ad.46.2025.05.23.10.14.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 May 2025 10:14:43 -0700 (PDT) Date: Fri, 23 May 2025 10:14:41 -0700 From: Deepak Gupta To: Alexandre Ghiti Cc: Andy Chiu , Ben Dooks , Cyril Bur , palmer@dabbelt.com, aou@eecs.berkeley.edu, paul.walmsley@sifive.com, charlie@rivosinc.com, jrtc27@jrtc27.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, jszhang@kernel.org, syzbot+e74b94fe601ab9552d69@syzkaller.appspotmail.com Subject: Re: [PATCH v6 1/5] riscv: save the SR_SUM status over switches Message-ID: References: <20250410070526.3160847-1-cyrilbur@tenstorrent.com> <20250410070526.3160847-2-cyrilbur@tenstorrent.com> <54d63ebf-b66f-41d4-85b1-ec0fa3401333@ghiti.fr> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <54d63ebf-b66f-41d4-85b1-ec0fa3401333@ghiti.fr> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250523_101445_691324_A633C94D X-CRM114-Status: GOOD ( 35.96 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gRnJpLCBNYXkgMjMsIDIwMjUgYXQgMDI6MjI6MjFQTSArMDIwMCwgQWxleGFuZHJlIEdoaXRp IHdyb3RlOgo+SGkgQW5keSwgRGVlcGFrLAo+Cj5PbiA1LzIzLzI1IDAwOjQzLCBEZWVwYWsgR3Vw dGEgd3JvdGU6Cj4+T24gRnJpLCBNYXkgMjMsIDIwMjUgYXQgMDE6NDI6NDlBTSArMDgwMCwgQW5k eSBDaGl1IHdyb3RlOgo+Pj5PbiBUaHUsIE1heSAyMiwgMjAyNSBhdCAxMTowOeKAr1BNIERlZXBh ayBHdXB0YSA8ZGVidWdAcml2b3NpbmMuY29tPiAKPj4+d3JvdGU6Cj4+Pj4KPj4+Pk9uIFRodSwg TWF5IDIyLCAyMDI1IGF0IDA3OjIzOjMyQU0gKzAxMDAsIEJlbiBEb29rcyB3cm90ZToKPj4+Pj5P biAyMC8wNS8yMDI1IDE3OjQ5LCBEZWVwYWsgR3VwdGEgd3JvdGU6Cj4+Pj4+PkkgZGlkIGdpdmUg dGhpcyBwYXRjaCBteSBSQiBhbmQgaGFkIHBsYW5uZWQgdG8gY29tZSBiYWNrIHRvIGl0IHRvIHNl ZQo+Pj4+Pj5pZiBpdCBpbXBhY3RzIGNmaSByZWxhdGVkIHBhdGNoZXMuIFRoYW5rcyB0byBhbGV4 IGZvciBicmluaWduZyB0byBteQo+Pj4+Pj5hdHRlbnRpb24gYWdhaW4uIEFzIGl0IHN0YW5kcyB0 b2RheSwgaXQgZG9lc24ndCBpbXBhY3QgY2ZpIHJlbGF0ZWQKPj4+Pj4+Y2hhbmdlcyBidXQgSSd2 ZSBzb21lIGNvbmNlcm5zLgo+Pj4+Pj4KPj4+Pj4+T3ZlcmFsbCBJIGRvIGFncmVlIHdlIHNob3Vs ZCByZWR1Y2UgbnVtYmVyIG9mIFNTVEFUVVMgYWNjZXNzZXMuCj4+Pj4+Pgo+Pj4+Pj5Db3VwbGUg b2YgcXVlc3Rpb25zIG9uIGludHJvZHVjaW5nIG5ldyBgc3N0YXR1c2AgZmllbGQgKGlubGluZSkK Pj4+Pj4+Cj4+Pj4+Pk9uIFR1ZSwgQXByIDIyLCAyMDI1IGF0IDA0OjAxOjM1UE0gLTA3MDAsIERl ZXBhayBHdXB0YSB3cm90ZToKPj4+Pj4+Pk9uIFRodSwgQXByIDEwLCAyMDI1IGF0IDA3OjA1OjIy QU0gKzAwMDAsIEN5cmlsIEJ1ciB3cm90ZToKPj4+Pj4+Pj5Gcm9tOiBCZW4gRG9va3MgPGJlbi5k b29rc0Bjb2RldGhpbmsuY28udWs+Cj4+Pj4+Pj4+Cj4+Pj4+Pj4+V2hlbiB0aHJlYWRzL3Rhc2tz IGFyZSBzd2l0Y2hlZCB3ZSBuZWVkIHRvIGVuc3VyZSB0aGUgb2xkIAo+Pj4+ZXhlY3V0aW9uJ3MK Pj4+Pj4+Pj5TUl9TVU0gc3RhdGUgaXMgc2F2ZWQgYW5kIHRoZSBuZXcgdGhyZWFkIGhhcyB0aGUg b2xkIFNSX1NVTSBzdGF0ZQo+Pj4+Pj4+PnJlc3RvcmVkLgo+Pj4+Pj4+Pgo+Pj4+Pj4+PlRoZSBp c3N1ZSB3YXMgc2VlbiB1bmRlciBoZWF2eSBsb2FkIGVzcGVjaWFsbHkgd2l0aCB0aGUgCj4+Pj5z eXotc3RyZXNzIHRvb2wKPj4+Pj4+Pj5ydW5uaW5nLCB3aXRoIGNyYXNoZXMgYXMgZm9sbG93cyBp biBzY2hlZHVsZV90YWlsOgo+Pj4+Pj4+Pgo+Pj4+Pj4+PlVuYWJsZSB0byBoYW5kbGUga2VybmVs IGFjY2VzcyB0byB1c2VyIG1lbW9yeSB3aXRob3V0IAo+Pj4+dWFjY2VzcyByb3V0aW5lcwo+Pj4+ Pj4+PmF0IHZpcnR1YWwgYWRkcmVzcyAwMDAwMDAwMDI3NDlmMGQwCj4+Pj4+Pj4+T29wcyBbIzFd Cj4+Pj4+Pj4+TW9kdWxlcyBsaW5rZWQgaW46Cj4+Pj4+Pj4+Q1BVOiAxIFBJRDogNDg3NSBDb21t OiBzeXotZXhlY3V0b3IuMCBOb3QgdGFpbnRlZAo+Pj4+Pj4+PjUuMTIuMC1yYzItc3l6a2FsbGVy LTAwNDY3LWcwZDc1ODhhYjllZjkgIzAKPj4+Pj4+Pj5IYXJkd2FyZSBuYW1lOiByaXNjdi12aXJ0 aW8scWVtdSAoRFQpCj4+Pj4+Pj4+ZXBjIDogc2NoZWR1bGVfdGFpbCsweDcyLzB4YjIga2VybmVs L3NjaGVkL2NvcmUuYzo0MjY0Cj4+Pj4+Pj4+cmEgOiB0YXNrX3BpZF92bnIgaW5jbHVkZS9saW51 eC9zY2hlZC5oOjE0MjEgW2lubGluZV0KPj4+Pj4+Pj5yYSA6IHNjaGVkdWxlX3RhaWwrMHg3MC8w eGIyIGtlcm5lbC9zY2hlZC9jb3JlLmM6NDI2NAo+Pj4+Pj4+PmVwYyA6IGZmZmZmZmUwMDAwOGM4 YjAgcmEgOiBmZmZmZmZlMDAwMDhjOGFlIHNwIDogZmZmZmZmZTAyNWQxN2VjMAo+Pj4+Pj4+Pmdw IDogZmZmZmZmZTAwNWQyNTM3OCB0cCA6IGZmZmZmZmUwMGYwZDAwMDAgdDAgOiAwMDAwMDAwMDAw MDAwMDAwCj4+Pj4+Pj4+dDEgOiAwMDAwMDAwMDAwMDAwMDAxIHQyIDogMDAwMDAwMDAwMDBmNDI0 MCBzMCA6IGZmZmZmZmUwMjVkMTdlZTAKPj4+Pj4+Pj5zMSA6IDAwMDAwMDAwMjc0OWYwZDAgYTAg OiAwMDAwMDAwMDAwMDAwMDJhIGExIDogMDAwMDAwMDAwMDAwMDAwMwo+Pj4+Pj4+PmEyIDogMWZm ZmZmZmMwY2ZhYzUwMCBhMyA6IGZmZmZmZmUwMDAwYzgwY2MgYTQgOiA1YWU5ZGI5MWMxOWJiZTAw Cj4+Pj4+Pj4+YTUgOiAwMDAwMDAwMDAwMDAwMDAwIGE2IDogMDAwMDAwMDAwMGYwMDAwMCBhNyA6 IGZmZmZmZmUwMDAwODJlYmEKPj4+Pj4+Pj5zMiA6IDAwMDAwMDAwMDAwNDAwMDAgczMgOiBmZmZm ZmZlMDBlZWY5NmMwIHM0IDogZmZmZmZmZTAyMmM3N2ZlMAo+Pj4+Pj4+PnM1IDogMDAwMDAwMDAw MDAwNDAwMCBzNiA6IGZmZmZmZmUwNjdkNzRlMDAgczcgOiBmZmZmZmZlMDY3ZDc0ODUwCj4+Pj4+ Pj4+czggOiBmZmZmZmZlMDY3ZDczZTE4IHM5IDogZmZmZmZmZTA2N2Q3NGUwMCBzMTA6IGZmZmZm ZmUwMGVlZjk2ZTgKPj4+Pj4+Pj5zMTE6IDAwMDAwMGFlNmNkZjgzNjggdDMgOiA1YWU5ZGI5MWMx OWJiZTAwIHQ0IDogZmZmZmZmYzQwNDNjYWZiMgo+Pj4+Pj4+PnQ1IDogZmZmZmZmYzQwNDNjYWZi YSB0NiA6IDAwMDAwMDAwMDAwNDAwMDAKPj4+Pj4+Pj5zdGF0dXM6IDAwMDAwMDAwMDAwMDAxMjAg YmFkYWRkcjogMDAwMDAwMDAyNzQ5ZjBkMCBjYXVzZToKPj4+Pj4+Pj4wMDAwMDAwMDAwMDAwMDBm Cj4+Pj4+Pj4+Q2FsbCBUcmFjZToKPj4+Pj4+Pj5bPGZmZmZmZmUwMDAwOGM4YjA+XSBzY2hlZHVs ZV90YWlsKzB4NzIvMHhiMiAKPj4+Pmtlcm5lbC9zY2hlZC9jb3JlLmM6NDI2NAo+Pj4+Pj4+Pls8 ZmZmZmZmZTAwMDAwNTU3MD5dIHJldF9mcm9tX2V4Y2VwdGlvbisweDAvMHgxNAo+Pj4+Pj4+PkR1 bXBpbmcgZnRyYWNlIGJ1ZmZlcjoKPj4+Pj4+Pj4gKGZ0cmFjZSBidWZmZXIgZW1wdHkpCj4+Pj4+ Pj4+LS0tWyBlbmQgdHJhY2UgYjVmOGY5MjMxZGM4N2RkYSBdLS0tCj4+Pj4+Pj4+Cj4+Pj4+Pj4+ VGhlIGlzc3VlIGNvbWVzIGZyb20gdGhlIHB1dF91c2VyKCkgaW4gc2NoZWR1bGVfdGFpbAo+Pj4+ Pj4+PihrZXJuZWwvc2NoZWQvY29yZS5jKSBkb2luZyB0aGUgZm9sbG93aW5nOgo+Pj4+Pj4+Pgo+ Pj4+Pj4+PmFzbWxpbmthZ2UgX192aXNpYmxlIHZvaWQgc2NoZWR1bGVfdGFpbChzdHJ1Y3QgdGFz a19zdHJ1Y3QgKnByZXYpCj4+Pj4+Pj4+ewo+Pj4+Pj4+Pi4uLgo+Pj4+Pj4+PsKgwqDCoMKgwqAg aWYgKGN1cnJlbnQtPnNldF9jaGlsZF90aWQpCj4+Pj4+Pj4+wqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqAgcHV0X3VzZXIodGFza19waWRfdm5yKGN1cnJlbnQpLCAKPj4+PmN1cnJlbnQtPnNldF9j aGlsZF90aWQpOwo+Pj4+Pj4+Pi4uLgo+Pj4+Pj4+Pn0KPj4+Pj4+Pj4KPj4+Pj4+Pj50aGUgcHV0 X3VzZXIoKSBtYWNybyBjYXVzZXMgdGhlIGNvZGUgc2VxdWVuY2UgdG8gY29tZSBvdXQgYXMgCj4+ Pj5mb2xsb3dzOgo+Pj4+Pj4+Pgo+Pj4+Pj4+PjE6wqDCoMKgIF9fZW5hYmxlX3VzZXJfYWNjZXNz KCkKPj4+Pj4+Pj4yOsKgwqDCoCByZWcgPSB0YXNrX3BpZF92bnIoY3VycmVudCk7Cj4+Pj4+Pj4+ MzrCoMKgwqAgKmN1cnJlbnQtPnNldF9jaGlsZF90aWQgPSByZWc7Cj4+Pj4+Pj4+NDrCoMKgwqAg X19kaXNhYmxlX3VzZXJfYWNjZXNzKCkKPj4+Pj4+Pj4KPj4+Pj4+Pj5UaGUgcHJvYmxlbSBpcyB0 aGF0IHdlIG1heSBoYXZlIGEgc2xlZXBpbmcgZnVuY3Rpb24gYXMgCj4+Pj5hcmd1bWVudCB3aGlj aAo+Pj4+Pj4+PmNvdWxkIGNsZWFyIFNSX1NVTSBjYXVzaW5nIHRoZSBwYW5pYyBhYm92ZS4gVGhp cyB3YXMgZml4ZWQgYnkKPj4+Pj4+Pj5ldmFsdWF0aW5nIHRoZSBhcmd1bWVudCBvZiB0aGUgcHV0 X3VzZXIoKSBtYWNybyBvdXRzaWRlIHRoZSAKPj4+PnVzZXItZW5hYmxlZAo+Pj4+Pj4+PnNlY3Rp b24gaW4gY29tbWl0IDI4NWE3NmJiMmNmNSAoInJpc2N2OiBldmFsdWF0ZSBwdXRfdXNlcigpIAo+ Pj4+YXJnIGJlZm9yZQo+Pj4+Pj4+PmVuYWJsaW5nIHVzZXIgYWNjZXNzIikiCj4+Pj4+Pj4+Cj4+ Pj4+Pj4+SW4gb3JkZXIgZm9yIHJpc2N2IHRvIHRha2UgYWR2YW50YWdlIG9mIHVuc2FmZV9nZXQv cHV0X1hYWCgpIAo+Pj4+bWFjcm9zIGFuZAo+Pj4+Pj4+PnRvIGF2b2lkIHRoZSBzYW1lIGlzc3Vl IHdlIGhhZCB3aXRoIHB1dF91c2VyKCkgYW5kIHNsZWVwaW5nIAo+Pj4+ZnVuY3Rpb25zIHdlCj4+ Pj4+Pj4+bXVzdCBlbnN1cmUgY29kZSBmbG93IGNhbiBnbyB0aHJvdWdoIHN3aXRjaF90bygpIGZy b20gd2l0aGluIAo+Pj4+YSByZWdpb24gb2YKPj4+Pj4+Pj5jb2RlIHdpdGggU1JfU1VNIGVuYWJs ZWQgYW5kIGNvbWUgYmFjayB3aXRoIFNSX1NVTSBzdGlsbCAKPj4+PmVuYWJsZWQuIFRoaXMKPj4+ Pj4+Pj5wYXRjaCBhZGRyZXNzZXMgdGhlIHByb2JsZW0gYWxsb3dpbmcgZnV0dXJlIHdvcmsgdG8g ZW5hYmxlIAo+Pj4+ZnVsbCB1c2Ugb2YKPj4+Pj4+Pj51bnNhZmVfZ2V0L3B1dF9YWFgoKSBtYWNy b3Mgd2l0aG91dCBuZWVkaW5nIHRvIHRha2UgYSBDU1IgCj4+Pj5iaXQgZmxpcCBjb3N0Cj4+Pj4+ Pj4+b24gZXZlcnkgYWNjZXNzLiBNYWtlIHN3aXRjaF90bygpIHNhdmUgYW5kIHJlc3RvcmUgU1Jf U1VNLgo+Pj4+Pj4+Pgo+Pj4+Pj4+PlJlcG9ydGVkLWJ5OiBzeXpib3QrZTc0Yjk0ZmU2MDFhYjk1 NTJkNjlAc3l6a2FsbGVyLmFwcHNwb3RtYWlsLmNvbQo+Pj4+Pj4+PlNpZ25lZC1vZmYtYnk6IEJl biBEb29rcyA8YmVuLmRvb2tzQGNvZGV0aGluay5jby51az4KPj4+Pj4+Pj5TaWduZWQtb2ZmLWJ5 OiBDeXJpbCBCdXIgPGN5cmlsYnVyQHRlbnN0b3JyZW50LmNvbT4KPj4+Pj4+Pj4tLS0KPj4+Pj4+ Pj5hcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL3Byb2Nlc3Nvci5oIHwgMSArCj4+Pj4+Pj4+YXJjaC9y aXNjdi9rZXJuZWwvYXNtLW9mZnNldHMuY8KgwqDCoCB8IDUgKysrKysKPj4+Pj4+Pj5hcmNoL3Jp c2N2L2tlcm5lbC9lbnRyeS5TwqDCoMKgwqDCoMKgwqDCoMKgIHwgOCArKysrKysrKwo+Pj4+Pj4+ PjMgZmlsZXMgY2hhbmdlZCwgMTQgaW5zZXJ0aW9ucygrKQo+Pj4+Pj4+Pgo+Pj4+Pj4+PmRpZmYg LS1naXQgYS9hcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL3Byb2Nlc3Nvci5oCj4+Pj4+Pj4+Yi9hcmNo L3Jpc2N2L2luY2x1ZGUvIGFzbS9wcm9jZXNzb3IuaAo+Pj4+Pj4+PmluZGV4IDVmNTZlYjlkMTE0 YS4uNThmZDExYzg5ZmU5IDEwMDY0NAo+Pj4+Pj4+Pi0tLSBhL2FyY2gvcmlzY3YvaW5jbHVkZS9h c20vcHJvY2Vzc29yLmgKPj4+Pj4+Pj4rKysgYi9hcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL3Byb2Nl c3Nvci5oCj4+Pj4+Pj4+QEAgLTEwMyw2ICsxMDMsNyBAQCBzdHJ1Y3QgdGhyZWFkX3N0cnVjdCB7 Cj4+Pj4+Pj4+wqDCoMKgIHN0cnVjdCBfX3Jpc2N2X2RfZXh0X3N0YXRlIGZzdGF0ZTsKPj4+Pj4+ Pj7CoMKgwqAgdW5zaWduZWQgbG9uZyBiYWRfY2F1c2U7Cj4+Pj4+Pj4+wqDCoMKgIHVuc2lnbmVk IGxvbmcgZW52Y2ZnOwo+Pj4+Pj4+PivCoMKgwqAgdW5zaWduZWQgbG9uZyBzdGF0dXM7Cj4+Pj4+ Pgo+Pj4+Pj5EbyB3ZSByZWFsbHkgbmVlZCBhIG5ldyBtZW1iZXIgZmllbGQgaW4gYHRocmVhZF9z dHJ1Y3RgLiBXZSAKPj4+PmFscmVhZHkgaGF2ZQo+Pj4+Pj5gc3N0YXR1c2AgaW4gYHB0X3JlZ3Ng IHdoaWNoIHJlZmxlY3RzIG92ZXJhbGwgZXhlY3V0aW9uIGVudmlyb25tZW50Cj4+Pj4+PnNpdHVh dGlvbgo+Pj4+Pj5mb3IgY3VycmVudCB0aHJlYWQuIFRoaXMgZ2V0cyBzYXZlZCBhbmQgcmVzdG9y ZWQgb24gdHJhcCBlbnRyeSAKPj4+PmFuZCBleGl0Lgo+Pj4+Pj4KPj4+Pj4+SWYgd2UgcHV0IGBz dGF0dXNgIGluIGB0aHJlYWRfc3RydWN0YCBpdCBjcmVhdGVzIGFtYmlndWl0eSBpbiB0ZXJtcwo+ Pj4+Pj5vZiB3aGljaAo+Pj4+Pj5gc3RhdHVzYCB0byBzYXZlIHRvIGFuZCBwaWNrIGZyb20gZnJv bSBmdXR1cmUgbWFpbnRhaW5pYmlsaXR5Cj4+Pj4+PnB1cnBvc2VzIGFzIHRoZQo+Pj4+Pj5maWVs ZHMgZ2V0IGludHJvZHVjZWQgdG8gdGhpcyBDU1IuCj4+Pj4+Pgo+Pj4+Pj5XaHkgY2FuJ3Qgd2Ug YWNjZXNzIGN1cnJlbnQgdHJhcCBmcmFtZSdzIGBzc3RhdHVzYCBpbWFnZSBpbgo+Pj4+Pj5gX19z d2l0Y2hfdG9gIHRvCj4+Pj4+PnNhdmUgYW5kIHJlc3RvcmU/Cj4+Pj4+Pgo+Pj4+Pj5MZXQgbWUg a25vdyBpZiBJIGFtIG1pc3Npbmcgc29tZXRoaW5nIG9idmlvdXMgaGVyZS4gSWYgdGhlcmUgaXMg YQo+Pj4+Pj5jb21wbGljYXRpb24sCj4+Pj4+PkkgYW0gbWlzc2luZyBoZXJlIGFuZCB3ZSBkbyBl bmQgdXAgdXNpbmcgdGhpcyBtZW1iZXIgZmllbGQsIEkgd291bGQKPj4+Pj4+cmVuYW1lIGl0Cj4+ Pj4+PnRvIHNvbWV0aGluZyBsaWtlIGBzdGF0dXNfa2VybmVsYCB0byByZWZsZWN0IHRoYXQuIFNv IHRoYXQgZnV0dXJlCj4+Pj4+PmNoYW5nZXMgYXJlCj4+Pj4+PmNvZ25pemFudCBvZiB0aGUgZmFj dCB0aGF0IHdlIGhhdmUgc3BsaXQgYHN0YXR1c2AuIE9uZSBmb3Iga2VybmVsCj4+Pj4+PmV4ZWN1 dGlvbiBlbnYKPj4+Pj4+cGVyIHRocmVhZCBhbmQgb25lIGZvciBjb250cm9sbGluZyB1c2VyIGV4 ZWN1dGlvbiBlbnYgcGVyIHRocmVhZC4KPj4+Pj4KPj4+Pj5UaGlzIGlzIHNvIGxvbmcgYWdvIG5v dyBJIGNhbm5vdCByZW1lbWJlciBpZiB0aGVyZSB3YXMgYW55IHNzdGF0dXMgaW4KPj4+Pj50aGUg cHRfcmVncyBmaWVsZCwKPj4+Pgo+Pj4+RlMvVlMgYml0cyBlbmNvZGUgc3RhdHVzIG9mIGZsb2F0 aW5nIHBvaW50IGFuZCB2ZWN0b3Igb24gCj4+Pj5wZXItdGhyZWFkIGJhc2lzLgo+Pj4+U28gYHN0 YXR1c2AgaGFzIGJlZW4gcGFydCBvZiBgcHRfcmVnc2AgZm9yIHF1aXRlIGEgd2hpbGUuCj4+Pj4K Pj4+Pj4gYW5kIGlmIGtlcm5lbCB0aHJlYWRzIGhhdmUgdGhlIHNhbWUgY29udGV4dCBhcyB0aGVp cgo+Pj4+PnVzZXJsYW5kIHBhcnRzLgo+Pj4+Cj4+Pj5JIGRpZG4ndCBtZWFuIGtlcm5lbCB0aHJl YWQuIFdoYXQgSSBtZWFudCB3YXMga2VybmVsIGV4ZWN1dGlvbiAKPj4+PmVudmlyb25tZW50Cj4+ Pj5wZXItdGhyZWFkLiBBIHVzZXJsYW5kIHRocmVhZCBkb2VzIHNwZW5kIHNvbWV0aW1lIGluIGtl cm5lbCBhbmQgCj4+Pj5rZXJuZWwgZG9lcwo+Pj4+dGhpbmdzIG9uIGl0cyBiZWhhbGYuIE9uZSBv ZiB0aG9zZSB0aGluZyBpcyB0b3VjaGluZyB1c2VyIG1lbW9yeSAKPj4+PmFuZCB0aGF0Cj4+Pj5y ZXF1aXJlcyBtdWNraW5nIHdpdGggdGhpcyBDU1IuIFNvIHdoYXQgSSBtZWFudCB3YXMgYXJlIHdl IAo+Pj4+c3BsaXR0aW5nIGBzdGF0dXNgCj4+Pj5vbiBwZXItdGhyZWFkIGJhc2lzIGZvciB0aGVp ciB0aW1lIHNwZW50IGluIHVzZXIgYW5kIGtlcm5lbC4KPj4+Pgo+Pj4+R2V0dGluZyBiYWNrIHRv IG9yaWdpbmFsIHF1ZXN0aW9uLS0KPj4+PkFzIEkgc2FpZCwgZWFjaCB0aHJlYWQgc3BlbmRzIHNv bWV0aW1lIGluIHVzZXIgb3IgaW4ga2VybmVsLiAKPj4+PmBzdGF0dXNgIGluCj4+Pj5gcHRfcmVn c2AgaXMgc2F2ZWQgb24gdHJhcCBlbnRyeSBhbmQgcmVzdG9yZWQgb24gdHJhcCBleGl0LiBJbiBh IHNlbnNlLAo+Pj4+YHN0YXR1c2AgZmllbGQgaW4gYHB0X3JlZ3NgIGlzIHJlZmxlY3RpbmcgZXhl Y3V0aW9uIHN0YXR1cyBvZiAKPj4+PnRoZSB0aHJlYWQgb24gcGVyCj4+Pj50cmFwIGJhc2lzLiBJ bnRyb2R1Y2luZyBgc3RhdHVzYCBpbiBgdGhyZWFkX3N0cnVjdGAgY3JlYXRlcyBhIAo+Pj4+Y29u ZnVzaW9uIChpZiBub3QKPj4+PmZvciB0b2RheSwgY2VydGFpbmx5IGZvciBmdXR1cmUpIG9mIHdo aWNoIGBzdGF0dXNgIHRvIHBpY2sgZnJvbSAKPj4+PndoZW4gd2UgYXJlCj4+Pj5kb2luZyBzYXZl L3Jlc3RvcmUuCj4+Pgo+Pj5JIGFncmVlIHRoYXQgaXQncyBhIGNvbmZ1c2lvbi4gc3N0YXR1cyBp cyBhbHJlYWR5IHNhdmVkIG9uIHB0X3JlZ3Mgb24KPj4+dHJhcCBlbnRyaWVzL3JldHVybiwgYWRk aW5nIGFub3RoZXIgZW50cnkgYWRkcyBjb2RlIGNvbXBsZXhpdHkgYW5kCj4+Pm1ha2VzIGRhdGEg aW5jb25zaXN0ZW50LiBCdXQsIHBlcmhhcHMgd2UnZCBldmVudHVhbGx5IG5lZWQgc29tZXRoaW5n Cj4+Pmxpa2UgdGhpcyAoSSB3aWxsIGV4cGxhaW4gd2h5KS4gU3RpbGwsIHRoZXJlIG1pZ2h0IGJl IGEgYmV0dGVyCj4+PmFwcHJvYWNoLgo+Pj4KPj4+WWVzLCB3ZSBjYW4gYWx3YXlzIHJlZmxlY3Qg cHRfcmVncyBmb3Igc3N0YXR1cy4gV2UgYWxsIGtub3cgdGhhdAo+Pj5wdF9yZWdzIHJlZmxlY3Rz IHNzdGF0dXMgYXQgdHJhcCBlbnRyeSwgYW5kIHRoZSBwdF9yZWdzIGF0IHNjaGVkdWxlcgo+Pj5w b2ludCByZWZlcnMgdG8gInVzZXIncyIgcHRfcmVncyB3aGVuZXZlciBpdCBmaXJzdCBlbnRlcnMg a2VybmVsIAo+Pj5tb2RlLiBIZXJlCj4+PmFyZSByZWFzb25zIHdoeSBTUl9TVU0gaGVyZSBtYXkg b3IgbWF5IG5vdCBiZSBwcm9wZXJseSB0cmFja2VkLiBGaXJzdCwKPj4+aWYgdGhpcyBpcyBhIHRy YXAgaW50cm9kdWNlZCBjb250ZXh0IHN3aXRjaCAoc3VjaCBhcyBpbnRlcnJ1cHRpbmcgaW4gYQo+ Pj5wcmVlbXB0aWJsZSBjb250ZXh0IGFmdGVyIHdlIG1hbnVhbGx5IGVuYWJsZSB1c2VyIGFjY2Vz cyBpbiBwdXRfdXNlciksCj4+PnRoZW4gU1JfU1VNIGlzIHNhdmVkIHNvbWV3aGVyZSBpbiB0aGUg a2VybmVsIHN0YWNrLCBhbmQgaXMgbm90Cj4+PnJlZmVyZW5jZS1hYmxlIHdpdGggdGFza19wdF9y ZWcgZHVyaW5nIGNvbnRleHQgc3dpdGNoLiBCdXQgd2UgYXJlIHNhZmUKPj4+YmVjYXVzZSB0aGUg dHJhcCBleGl0IGFzbSB3b3VsZCBoZWxwIHVzIHJlc3RvcmUgdGhlIGNvcnJlY3QgU1JfU1VNCj4+ PmJhY2suIEhvd2V2ZXIsIGlmIHRoaXMgaXMgYSBzZWxmLWluaXRpYXRpbmcgY29udGV4dCBzd2l0 Y2ggKGNhbGxpbmcKPj4+aW50byBzY2hlZHVsZSgpKSwgdGhlbiBTUl9TVU0gaXMgbm90IHNhdmVk IGFueXdoZXJlLCBhbmQgcG9zc2libHkKPj4+Y2F1c2luZyB0aGlzIGVycm9yLgo+Pj4KPj4+UHJl ZW1wdGlibGUgVmVjdG9yIGluIHRoZSBrZXJuZWwgbW9kZSBhbHNvIGhhZCB0aGlzIHByb2JsZW0g d2hlcmUgYQo+Pj5zZWxmLWluaXRpYXRpbmcgY29udGV4dCBzd2l0Y2ggbG9zZXMgdGhlIHRyYWNr IG9mIHNzdGF0dXMudnMuIFRoZSB3YXkKPj4+SSBtYW5hZ2VkIGl0IGlzIHRvIHRyYWNrIHRoZSBW UyBiaXQgYXQgY29udGV4dCBzd2l0Y2ggdGltZS4gSG93ZXZlciwKPj4+dGhpcyBidWcgc2hvd3Mg dGhhdCBwZW9wbGUgYXJlIHJlcGVhdGVkbHkgZmFjaW5nIHRoZSBwcm9ibGVtLCBhbmQKPj4+bWF5 YmUgaXQgc3VnZ2VzdHMgdGhhdCB3ZSdkIG5lZWQgYSBiZXR0ZXIgd2F5IG9mIG1hbmFnaW5nIHNz dGF0dXMKPj4+YWNyb3NzIGNvbnRleHQgc3dpdGNoZXMuIEdpdmVuIHRoZSBjb21wbGV4IG5hdHVy ZSBvZiB0aGlzIHJlZ2lzdGVyLAo+Pj53aGljaCBhbHNvIHRvdWNoZXMgdGhlIGludGVycnVwdCBl bmFibGUgc3RhdHVzLCBJIGRvbid0IHRoaW5rIG5haXZlbHkKPj4+c2F2aW5nL3Jlc3RvcmluZyB0 aGUgZW50aXJlIHJlZ2lzdGVyIGlzIHRoZSB3YXkgdG8gZ28uIE1heWJlIHRoZQo+Pj52YXJpYWJs ZSBkZXNlcnZlcyBhIG1vcmUgc3BlY2lmaWMgbmFtaW5nIGFuZCBkb2N1bWVudGF0aW9uLiBBbmQg aWYKPj4+d2UnZCBuZWVkIGEgY2VudHJhbGl6ZWQgcGxhY2UgZm9yIG1hbmFnaW5nIHRoZXNlIHN0 YXR1c2VzLCB0aGVuIGl0Cj4+PmFsc28gaGFzIHRvIHRha2UgY2FyZSBvZiBzc3RhdHVzLlZTLgo+ Cj4KPkFuZHksIHRoYW5rcyBmb3IgdGhlIHByZWNpc2UgZXhwbGFuYXRpb24gb2YgdGhlIHByb2Js ZW0gOikKPgo+U28gaXQgdG9vayBtZSBzb21lIHRpbWUgYnV0IGhlcmUgYXJlIG15IHRob3VnaHRz IG9uIHRoaXMuIFdlIHNob3VsZCAKPnRyZWF0IHB0X3JlZ3MgYW5kIHRocmVhZF9zdHJ1Y3QgZGlm ZmVyZW50bHkgYXMgdGhleSBkbyBub3QgcmVwcmVzZW50IAo+dGhlIHNhbWUgdGhpbmc6Cj4tIHB0 X3JlZ3MgcmVwcmVzZW50cyB0aGUgY29udGV4dCBvZiBhIHRocmVhZCB3aGVuIGl0IHRha2VzIGEg dHJhcAo+LSB0aHJlYWRfc3RydWN0IHJlcHJlc2VudHMgYSAia2VybmVsLWluZHVjZWQiIChvciBh ICJpbi1rZXJuZWwiKSAKPmNvbnRleHQgbm90IGNhdXNlZCBieSB0cmFwcwoKRXhhY3RseSB0aGV5 IHJlcHJlc2VudCBkaWZmZXJlbnQgY29udGV4dCBvZiBleGVjdXRpb24uIFRyYXAgcmVwcmVzZW50 cyBhCm5vbi1saW5lYXIgY29udHJvbCBmbG93IGNoYW5nZSBhbmQgdGh1cyBhIGZyZXNoIHN0YXJ0 IG9mIGV4ZWN1dGlvbiBjb250cm9sCmZsb3cgaW50byBrZXJuZWwgd2hpbGUgYGtlcm5lbC1pbmR1 Y2VkYCBvbmUncyBhcmUgYWdhaW4gbm9uLWxpbmVhciBidXQKZnVsbHkgYSBrZXJuZWwvc29mdHdh cmUgY29uc3RydWN0LgoKQSBmcmVzaCB0cmFwcGVkIGV4ZWN1dGlvbiBjb250ZXh0IHNob3VsZG4n dCBoYXZlIFNVTSBzZXQgd2hpY2ggaXMgaG93IGl0IGlzCmN1cnJlbnRseSBpbiBrZXJuZWwuIFRo aXMgYml0IGdldHMgY2xlYXJlZCBpbiB0cmFwIGVudHJ5IGFuZCBgc3N0YXR1c2AgZ2V0cwpzYXZl ZCBpbiBgcHRfcmVnc2AgKGluY2x1ZGluZyBTUl9JRSkgc28gdGhhdCBpdCBjb3VsZCBiZSByZXN0 b3JlZCB3aGVuZXZlcgpgc3JldGAgaGFwcGVucy4KClRoZSBwcm9ibGVtIHdlJ2FyZSBzZWVpbmcg aGVyZSBpcyB0d28gZm9sZC0tCgoxKSBXZSBkb24ndCB3YW50IHRvIHNldCBhbmQgY2xlYXIgd2hl biB3ZSBhcmUgYWNjZXNzaW5nIGFycmF5L3N0cmluZyBmb3IgZWFjaAogICAgd29yZC4gVGhpcyBp cyBzb2Z0d2FyZSBwcm9ibGVtIGFuZCB0aGlzIGVudGlyZSBzZXJpZXMgaXMgYWRkcmVzc2luZyBp dC4KCjIpIFRvIGF2b2lkIGZpcnN0IHByb2JsZW0gd2UgYXJlIG9wdGltaXppbmcgdGhlIGFjY2Vz cyB0byBDU1IgYnkgc2V0dGluZyBpdAogICAgb25jZSBhbmQgY2xlYXJpbmcgaXQgb25jZS4gQnV0 IG5vdyB3ZSBkb24ndCB3YW50IHRvIGxvb3NlIHRoaXMgYml0IGlmIHRoZXJlCiAgICB3ZXJlOgoK CWEpIHRyYXAgaW4gYmV0d2VlbiAKICAgICAgICAgYikga2VybmVsIGluZHVjZWQgc2NoZWR1bGUg b3V0CiAgICAgICAgIGMpIGEpIGZvbGxvd2VkIGJ5IGIpCiAgICAgICAgIGQpIGEpIGZvbGxvd2Vk IGJ5IGFub3RoZXIgYSkKICAgICAgICAgZSkgbmVzdGVkIHRyYXBzCgpJZiBhKSBvY2N1cnMsIHdl IGFyZSBkZWZpbml0bGV5IGxvb3NpbmcgdGhlIGJpdCBhcyBwZXIgY3VycmVudCBjb2RlLiBJZiBi KQpoYXBwZW5zIHRoZW4gYWxzbyB0aGUgc2FtZSBzaXR1YXRpb24uCgpTYXZpbmcgaXQgaW4gYHRo cmVhZF9zdHJ1Y3RgIG9ubHkgYWRkcmVzc2VzIGBiYC4gQW5kIG5vdCBgYWAsIGBjYCwgYGRgIGFu ZApgZWAuIElNSE8gYGVgIGlzIGZhci1mZXRjaGVkIHNpdHVhdGlvbiBidXQgSSBiZWxpZXZlIGBh YCwgYGJgLCBgY2AgYW5kIGBkYCBoYXBwZW4KZHVyaW5nIG5vcm1hbCBydW50aW1lIG9mIGtlcm5l bC4KClNvIGl0IGFsbCBkZXBlbmRzIG9uIG5lc3RpbmcgbGV2ZWwgb2YgdHJhcHMgc3VwcG9ydGVk IGJ5IHJpc2N2IGtlcm5lbC4KCklsbHVzdHJhaW5nIGBjICsgZGAgZXhhbXBsZSwgaWYga2VybmVs IGNhbiB0YWtlIDIgbmVzdGVkIGxldmVsIG9mIHRyYXBzIHdpdGgKZmlyc3QgdHJhcCBjb250ZXh0 IGhhdmluZyBoYWQgdGhlIFNVTSBiaXQgc2V0LCBidXQgdGhlIHNlY29uZCB0cmFwIGhhZCBpdCBj bGVhcgphbmQgbm93IGNvbWVzIHRoZSBzd2l0Y2ggb3V0IG9mIHRoaXMgdGhyZWFkLCBhdCB0aGlz IHBvaW50IGlmIGl0IHdlcmUgc2F2ZWQgaW4KYHRocmVhZF9zdHJ1Y3RgIFNVTSB3b3VsZCBiZSBs b3N0IGZvciB0aGUgZmlyc3QgdHJhcC4KCkxhdGVyIHdoZW4gdGhlIHRocmVhZCBnZXRzIHN3aXRj aGVkIGluIGFnYWluLCB5b3Ugd291bGQgZ28gaW4gMm5kIHRyYXAKY29udGV4dCB3aXRob3V0IFNV TSAoYmVjYXVzZSBgdGhyZWFkX2NvbnRleHRgIGRpZG50IGhhZCBpdCBzYXZlZCksIHdoaWNoIGlz CmZpbmUuIEFsdGhvdWdoIHdoZW4gMm5kIHRyYXAgY29udGV4dCBldmVudHVhbGx5IHBlcmZvcm1z IGBzcmV0YCwgaXQgd2lsbApnbyBiYWNrIHRvIGZpcnN0IHRyYXAgY29udGV4dCB3aGVyZSBTVU0g d2FzIGV4cGVjdGVkIHRvIGJlIHNldCBiZWNhdXNlIGl0CnRvdWNoaW5nIGEgdXNlciBtZW1vcnku CgpBIGdvb2QgZXhhbXBsZSB3b3VsZCBiZSBhIHN5c2NhbGwsIHNvIHRoYXQncyB0aGUgZmlyc3Qg dHJhcC4gU1VNIGJpdCBpcyBzZXQsCnRvdWNoZWQgdXNlciBtZW1vcnkgYW5kIHRvb2sgYSB0cmFw IChwYWdlIGZhdWx0KS4gTm93IGNvZGUgaXMgaW4gc2Vjb25kIHRyYXAKd2hpY2ggc2hvdWxkIGNs ZWFyIHRoZSBTVU0gYml0LiBTb21ld2hlcmUgaW4gbWVtb3J5IG1hbmFnZXIgc3RhY2ssIHRocmVh ZCBpcwpzY2hlZHVsZWQgb3V0IGFuZCBub3cgYHNzdGF0dXNgIGlzIHNhdmVkIGluIGB0aHJlYWRf c3RydWN0YC4gVGhpcyBpcyBvbmx5CnNlcnZpbmcgY3VycmVudCB0cmFwIGNvbnRleHQgbmVlZHMg YW5kIG5vdCB0aGUgb25lIHdoZXJlIGBTVU1gIG5lZWRlZCB0byBiZQpzZXQuCgpXZSBjYW4gc3Vw cG9ydCBzdWNoIG5lc3Rpbmcgb25seSBieSBlbnN1cmluZyBiZWxvdwoKT24gdHJhcCBlbnRyeSBk byAKLSBzYXZlIGBzdGF0dXNgIGluIGBwdF9yZWdzYCBvciBzb21lIG90aGVyIEZJTE8gZGF0YSBz dHJ1Y3R1cmUKLSBjbGVhciBTVU0gKGFuZCBvdGhlciBiaXRzIG5lZWRlZCB0byBiZSBjbGVhcmVk KQoKT24gdHJhcCByZXR1cm4gZG8KLSByZWxvYWQgYHN0YXR1c2AgZnJvbSBgcHRfcmVnc2Agb3Ig c29tZSBGSUxPIGRhdGEgc3RydWN0dXJlCgpRdWl0ZSBhbmFsb2dvdXMgdG8gd2hhdCB3ZSBkbyBm b3IgU1JfSUUgYXMgd2VsbC4KCj4KPlRoYXQncyB3aHkgSSBkb24ndCByZWFsbHkgbGlrZSBEZWVw YWsncyBwcm9wb3NhbCBiZWxvdyBhcyBpdCBtaXhlcyAKPmJvdGggYW5kIEkgZmluZCBpdCB0cmlj a3kuCj4KPkkgY2FuJ3QgZmluZCBhIHNpdHVhdGlvbiB3aGVyZSBzYXZpbmcvcmVzdG9yaW5nIHRo ZSBlbnRpcmUgc3N0YXR1cyBhdCAKPmNvbnRleHQtc3dpdGNoIGlzIGEgcHJvYmxlbSB0aG91Z2gs IGRvZXMgYW55b25lIGhhdmUgc3VjaCB0aGluZyBpbiAKPm1pbmQ/Cj4KPkZpbmFsbHkgSSB1bmRl cnN0YW5kIHRoYXQgaGF2aW5nIGFub3RoZXIgY29weSBvZiBzc3RhdHVzIGluIAo+dGhyZWFkX3N0 cnVjdCBpcyBub3QgaW50dWl0aXZlIGFuZCB3ZSBzaG91bGQsIGVpdGhlciBleHBsYWluIHdoeSBv ciAKPm9ubHkgc3RvcmUgdGhlIFNVTSBiaXQgKGxpa2UgZm9yIHNzdGF0dXMuVlMpLgo+Cj5QbGVh c2UgY29udGludWUgdGhlIGRpc2N1c3Npb24gYXMgd2UgbmVlZCB0byBmaW5kIGEgc29sdXRpb24g dGhhdCAKPnBsZWFzZXMgZXZlcnlvbmUgc29vbiA6KQo+Cj5UaGFua3MgYWxsIGZvciBqdW1waW5n IGluLAo+Cj5BbGV4Cj4KPgo+Pgo+Pgo+PklNSE8sIHRoZSBwcm9ibGVtIHdlIGFyZSB0cnlpbmcg dG8gc29sdmUgaW4gdGhpcyBwYXRjaCBpcyBlYXNpbHkgCj4+c29sdmFibGUgaW4KPj5iZWxvdyBt YW5uZXIuCj4+Cj4+Cj4+ZGlmZiAtLWdpdCBhL2FyY2gvcmlzY3YvaW5jbHVkZS9hc20vc3dpdGNo X3RvLmggCj4+Yi9hcmNoL3Jpc2N2L2luY2x1ZGUvYXNtL3N3aXRjaF90by5oCj4+aW5kZXggMGU3 MWViODJmOTIwLi40OTlkMDBhNmZiNjcgMTAwNjQ0Cj4+LS0tIGEvYXJjaC9yaXNjdi9pbmNsdWRl L2FzbS9zd2l0Y2hfdG8uaAo+PisrKyBiL2FyY2gvcmlzY3YvaW5jbHVkZS9hc20vc3dpdGNoX3Rv LmgKPj5AQCAtNTgsNiArNTgsMjAgQEAgc3RhdGljIGlubGluZSB2b2lkIF9fc3dpdGNoX3RvX2Zw dShzdHJ1Y3QgCj4+dGFza19zdHJ1Y3QgKnByZXYsCj4+wqDCoMKgwqDCoMKgwqAgZnN0YXRlX3Jl c3RvcmUobmV4dCwgdGFza19wdF9yZWdzKG5leHQpKTsKPj7CoH0KPj4KPj4rc3RhdGljIGlubGlu ZSB2b2lkIF9fc3dpdGNoX3RvX3N0YXR1cyhzdHJ1Y3QgdGFza19zdHJ1Y3QgKnByZXYsCj4+K8Kg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoCBzdHJ1Y3QgdGFza19zdHJ1Y3QgKm5leHQpCj4+K3sKPj4rwqDCoMKgwqDCoMKgIHN0 cnVjdCBwdF9yZWdzICpyZWdzOwo+PisKPj4rwqDCoMKgwqDCoMKgIC8qIHNhdmUgc3RhdHVzICov Cj4+K8KgwqDCoMKgwqDCoCByZWdzID0gdGFza19wdF9yZWdzKHByZXYpOwo+PivCoMKgwqDCoMKg wqAgcmVncy0+c3RhdHVzID0gY3NyX3JlYWQoQ1NSX1NUQVRVUyk7Cj4+Kwo+PivCoMKgwqDCoMKg wqAgLyogcmVzdG9yZSBzdGF0dXMgKi8KPj4rwqDCoMKgwqDCoMKgIHJlZ3MgPSB0YXNrX3B0X3Jl Z3MobmV4dCk7Cj4+K8KgwqDCoMKgwqDCoCBjc3Jfd3JpdGUoQ1NSX1NUQVRVUywgcmVncy0+c3Rh dHVzKTsKPj4rfQo+PisKPj7CoHN0YXRpYyBfX2Fsd2F5c19pbmxpbmUgYm9vbCBoYXNfZnB1KHZv aWQpCj4+wqB7Cj4+wqDCoMKgwqDCoMKgwqAgcmV0dXJuIHJpc2N2X2hhc19leHRlbnNpb25fbGlr ZWx5KFJJU0NWX0lTQV9FWFRfZikgfHwKPj5AQCAtMTE1LDYgKzEyOSw3IEBAIGRvIAo+PnvCoMKg wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBcCj4+wqDC oMKgwqDCoMKgwqAgc3RydWN0IHRhc2tfc3RydWN0ICpfX3ByZXYgPSAocHJldik7wqDCoMKgwqDC oMKgwqDCoMKgwqDCoCBcCj4+wqDCoMKgwqDCoMKgwqAgc3RydWN0IHRhc2tfc3RydWN0ICpfX25l eHQgPSAobmV4dCk7wqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBcCj4+wqDCoMKgwqDCoMKgwqAgX19z ZXRfcHJldl9jcHUoX19wcmV2LT50aHJlYWQpO8KgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgIFwKPj4rwqDCoMKgwqDCoMKgIF9fc3dpdGNoX3RvX3N0YXR1cyhfX3ByZXYsIF9fbmV4dCnC oMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBcCj4+wqDCoMKgwqDCoMKgwqAgaWYgKGhhc19mcHUo KSnCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqAgXAo+PsKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCBfX3N3aXRjaF90 b19mcHUoX19wcmV2LCBfX25leHQpO8KgwqDCoMKgwqDCoMKgIFwKPj7CoMKgwqDCoMKgwqDCoCBp ZiAoaGFzX3ZlY3RvcigpIHx8IGhhc194dGhlYWR2ZWN0b3IoKSnCoMKgwqDCoMKgwqDCoMKgIFwK Pj5kaWZmIC0tZ2l0IGEvYXJjaC9yaXNjdi9rZXJuZWwvZW50cnkuUyBiL2FyY2gvcmlzY3Yva2Vy bmVsL2VudHJ5LlMKPj5pbmRleCA4ZDI1ODM3YTkzODQuLmEzYjk4YzFiZTA1NSAxMDA2NDQKPj4t LS0gYS9hcmNoL3Jpc2N2L2tlcm5lbC9lbnRyeS5TCj4+KysrIGIvYXJjaC9yaXNjdi9rZXJuZWwv ZW50cnkuUwo+PkBAIC0xNjIsMTcgKzE2Miw4IEBAIFNZTV9DT0RFX1NUQVJUKGhhbmRsZV9leGNl cHRpb24pCj4+wqDCoMKgwqDCoMKgwqAgUkVHX1MgeDUswqAgUFRfVDAoc3ApCj4+wqDCoMKgwqDC oMKgwqAgc2F2ZV9mcm9tX3g2X3RvX3gzMQo+Pgo+Pi3CoMKgwqDCoMKgwqAgLyoKPj4twqDCoMKg wqDCoMKgwqAgKiBEaXNhYmxlIHVzZXItbW9kZSBtZW1vcnkgYWNjZXNzIGFzIGl0IHNob3VsZCBv bmx5IGJlIHNldCAKPj5pbiB0aGUKPj4twqDCoMKgwqDCoMKgwqAgKiBhY3R1YWwgdXNlciBjb3B5 IHJvdXRpbmVzLgo+Pi3CoMKgwqDCoMKgwqDCoCAqCj4+LcKgwqDCoMKgwqDCoMKgICogRGlzYWJs ZSB0aGUgRlBVL1ZlY3RvciB0byBkZXRlY3QgaWxsZWdhbCB1c2FnZSBvZiAKPj5mbG9hdGluZyBw b2ludAo+Pi3CoMKgwqDCoMKgwqDCoCAqIG9yIHZlY3RvciBpbiBrZXJuZWwgc3BhY2UuCj4+LcKg wqDCoMKgwqDCoMKgICovCj4+LcKgwqDCoMKgwqDCoCBsaSB0MCwgU1JfU1VNIHwgU1JfRlNfVlMg fCBTUl9FTFAKPj4tCj4+wqDCoMKgwqDCoMKgwqAgUkVHX0wgczAsIFRBU0tfVElfVVNFUl9TUCh0 cCkKPj4twqDCoMKgwqDCoMKgIGNzcnJjIHMxLCBDU1JfU1RBVFVTLCB0MAo+PivCoMKgwqDCoMKg wqAgY3NyciBzMSwgQ1NSX1NUQVRVUwo+PsKgwqDCoMKgwqDCoMKgIHNhdmVfdXNlcnNzcCBzMiwg czEKPj7CoMKgwqDCoMKgwqDCoCBjc3JyIHMyLCBDU1JfRVBDCj4+wqDCoMKgwqDCoMKgwqAgY3Ny ciBzMywgQ1NSX1RWQUwKPj5AQCAtMTg1LDYgKzE3NiwxNiBAQCBTWU1fQ09ERV9TVEFSVChoYW5k bGVfZXhjZXB0aW9uKQo+PsKgwqDCoMKgwqDCoMKgIFJFR19TIHM0LCBQVF9DQVVTRShzcCkKPj7C oMKgwqDCoMKgwqDCoCBSRUdfUyBzNSwgUFRfVFAoc3ApCj4+Cj4+K8KgwqDCoMKgwqDCoCAvKgo+ PivCoMKgwqDCoMKgwqDCoCAqIEl0IGlzIGZyZXNoIHRyYXAgZW50cnkuIERpc2FibGUgdXNlci1t b2RlIG1lbW9yeSBhY2Nlc3MgCj4+YXMgaXQgc2hvdWxkIG9ubHkgYmUgc2V0IGluIHRoZQo+PivC oMKgwqDCoMKgwqDCoCAqIGFjdHVhbCB1c2VyIGNvcHkgcm91dGluZXMuCj4+K8KgwqDCoMKgwqDC oMKgICoKPj4rwqDCoMKgwqDCoMKgwqAgKiBEaXNhYmxlIHRoZSBGUFUvVmVjdG9yIHRvIGRldGVj dCBpbGxlZ2FsIHVzYWdlIG9mIAo+PmZsb2F0aW5nIHBvaW50Cj4+K8KgwqDCoMKgwqDCoMKgICog b3IgdmVjdG9yIGluIGtlcm5lbCBzcGFjZS4KPj4rwqDCoMKgwqDCoMKgwqAgKi8KPj4rwqDCoMKg wqDCoMKgIGxpIHQwLCBTUl9TVU0gfCBTUl9GU19WUyB8IFNSX0VMUAo+PivCoMKgwqDCoMKgwqAg Y3NycmMgczEsIENTUl9TVEFUVVMsIHQwCj4+Kwo+PsKgwqDCoMKgwqDCoMKgIC8qCj4+wqDCoMKg wqDCoMKgwqDCoCAqIFNldCB0aGUgc2NyYXRjaCByZWdpc3RlciB0byAwLCBzbyB0aGF0IGlmIGEg cmVjdXJzaXZlIAo+PmV4Y2VwdGlvbgo+PsKgwqDCoMKgwqDCoMKgwqAgKiBvY2N1cnMsIHRoZSBl eGNlcHRpb24gdmVjdG9yIGtub3dzIGl0IGNhbWUgZnJvbSB0aGUga2VybmVsCj4+Cj4+Cj4+Cj4+ RHVyaW5nIHRoZSB0aW1lIHNwZW50IGluIGtlcm5lbCBpZiBzZXRzIFNVTSBiaXQgaW4gc3RhdHVz IHRoZW4sIGFib3ZlCj4+YF9fc3dpdGNoX3RvX3N0YXR1c2Agd2lsbCBlbnN1cmUgdGhhdCBgc3Rh dHVzYCB3aWxsIGdldCBzYXZlZCBmb3IgY3VycmVudAo+PnRocmVhZCBhbmQgcmVzdG9yZWQgZm9y IG5leHQgdGhyZWFkLgo+Pgo+PkZ1cnRoZXJtb3JlLCBjdXJyZW50IHRyYXAgZW50cnkgY29kZSBj bGVhcnMgRlMvVlMvU1VNIChmb3IgcmlnaHQgCj4+cmVhc29ucykuIEl0Cj4+cmVwcmVzZW50cyBu b24tbGluZWFyIGNoYW5nZSBvZiBjb250cm9sIGZsb3cgYW5kIHRodXMgd2hhdGV2ZXIgd2lsbCAK Pj5leGVjdXRlIG5leHQKPj5zaG91bGRuJ3QgbmVlZCBTVU0vRlMvVlMgdW5sZXNzIGl0IHdhbnRz IHRvIHNldCBpdCkuIFRoaXMgcGF0Y2ggc2xpZ2h0bHkKPj5tb2RpZmllcyB0aGUgZmxvdyBieSBm aXJzdCBzYXZpbmcgdGhlIGBzdGF0dXNgIG9uIHRyYXAgZnJhbWUgKHRodXMgCj4+aWYgcHJldmlv dXMKPj50cmFwIGZyYW1lIGhhZCBTVU09MSwgaXQgd2lsbCBiZSBzYXZlZCBhbmQgcmVzdG9yZWQp LiBBbmQgdGhlbiBpdAo+PnVuY29uZGl0aW9uYWxseSBjbGVhcnMgdGhlIFNVTS9GUy9WUyB0byBl bnN1cmUgdGhhdCB0aGlzIG5ldyB0cmFwIAo+PmNvbnRleHQgcnVucwo+PndpdGhvdXQgbmVlZGlu ZyBTVU09MS4gVGhpcyBlbnN1cmVzIG5lc3Rpbmcgb2YgdHJhcCBmcmFtZXMgd2l0aG91dCAKPj5k aWx1dGluZwo+PnNlY3VyaXR5IHByb3BlcnRpZXMgb2YgU1VNLgo+Pgo+Pj4KPj4+VGhhbmtzLAo+ Pj5BbmR5Cj4+Pgo+Pj4KPj4+Cj4+Pgo+Pj4+Cj4+Pj5TbyBteSBmaXJzdCBxdWVzdGlvbiB3YXMg d2h5IG5vdCB0byB1c2UgYHN0YXR1c2AgaW4gYHB0X3JlZ3NgLiAKPj4+Pkl0IGlzIGdyYW51bGFy Cj4+Pj5hcyBpdCBjYW4gZ2V0IChpdCBpcyBhdmFpbGFibGUgcGVyIHRocmVhZCBjb250ZXh0IHBl ciB0cmFwIGJhc2lzKS4KPj4+Pgo+Pj4+Cj4+Pj5JIGRpZCBhc2sgQWxleCBhcyB3ZWxsLiBJJ2xs IHBpbmcgaGltIGFnYWluLgo+Pj4+Cj4+Pj4+Cj4+Pj4+RG9lcyBhbnlvbmUgZWxzZSBoYXZlIGFu eSBjb21tZW50IG9uIHRoaXM/Cj4+Pj4+Cj4+Pj4+Pgo+Pj4+Pj4+PsKgwqDCoCB1MzIgcmlzY3Zf dl9mbGFnczsKPj4+Pj4+Pj7CoMKgwqAgdTMyIHZzdGF0ZV9jdHJsOwo+Pj4+Pj4+PsKgwqDCoCBz dHJ1Y3QgX19yaXNjdl92X2V4dF9zdGF0ZSB2c3RhdGU7Cj4+Pj4+Pj4+ZGlmZiAtLWdpdCBhL2Fy Y2gvcmlzY3Yva2VybmVsL2FzbS1vZmZzZXRzLmMKPj4+Pj4+Pj5iL2FyY2gvcmlzY3Yva2VybmVs L2FzbS0gb2Zmc2V0cy5jCj4+Pj4+Pj4+aW5kZXggMTY0OTA3NTUzMDRlLi45NjljNjViMWZlNDEg MTAwNjQ0Cj4+Pj4+Pj4+LS0tIGEvYXJjaC9yaXNjdi9rZXJuZWwvYXNtLW9mZnNldHMuYwo+Pj4+ Pj4+PisrKyBiL2FyY2gvcmlzY3Yva2VybmVsL2FzbS1vZmZzZXRzLmMKPj4+Pj4+Pj5AQCAtMzQs NiArMzQsNyBAQCB2b2lkIGFzbV9vZmZzZXRzKHZvaWQpCj4+Pj4+Pj4+wqDCoMKgIE9GRlNFVChU QVNLX1RIUkVBRF9TOSwgdGFza19zdHJ1Y3QsIHRocmVhZC5zWzldKTsKPj4+Pj4+Pj7CoMKgwqAg T0ZGU0VUKFRBU0tfVEhSRUFEX1MxMCwgdGFza19zdHJ1Y3QsIHRocmVhZC5zWzEwXSk7Cj4+Pj4+ Pj4+wqDCoMKgIE9GRlNFVChUQVNLX1RIUkVBRF9TMTEsIHRhc2tfc3RydWN0LCB0aHJlYWQuc1sx MV0pOwo+Pj4+Pj4KPj4+Pj4+X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX18KPj4+Pj4+bGludXgtcmlzY3YgbWFpbGluZyBsaXN0Cj4+Pj4+PmxpbnV4LXJpc2N2 QGxpc3RzLmluZnJhZGVhZC5vcmcKPj4+Pj4+aHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFp bG1hbi9saXN0aW5mby9saW51eC1yaXNjdgo+Pj4+Pj4KPj4+Pj4KPj4+Pj4KPj4+Pj4tLQo+Pj4+ PkJlbiBEb29rcyBodHRwOi8vd3d3LmNvZGV0aGluay5jby51ay8KPj4+Pj5TZW5pb3IgRW5naW5l ZXLCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoCBDb2RldGhpbmsgLSAKPj4+PlByb3ZpZGluZyBHZW5pdXMKPj4+Pj4KPj4+Pj5odHRw czovL3d3dy5jb2RldGhpbmsuY28udWsvcHJpdmFjeS5odG1sCj4+Pj4KPj4+Pl9fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCj4+Pj5saW51eC1yaXNjdiBtYWls aW5nIGxpc3QKPj4+PmxpbnV4LXJpc2N2QGxpc3RzLmluZnJhZGVhZC5vcmcKPj4+Pmh0dHA6Ly9s aXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtcmlzY3YKPj4KPj5fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwo+PmxpbnV4LXJpc2N2 IG1haWxpbmcgbGlzdAo+PmxpbnV4LXJpc2N2QGxpc3RzLmluZnJhZGVhZC5vcmcKPj5odHRwOi8v bGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LXJpc2N2CgpfX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1yaXNjdiBtYWls aW5nIGxpc3QKbGludXgtcmlzY3ZAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5m cmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LXJpc2N2Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f175.google.com (mail-pl1-f175.google.com [209.85.214.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DF62297B89 for ; Fri, 23 May 2025 17:14:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.175 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748020488; cv=none; b=n9frB3HwfvPIxKLPJwBFDVbIO5wJRBwZGm/18YQQ1R7eIKv1QCerLDUGc5zyyJ0jTm32wVhKjmi5tTca7/CFjgsdB75OeJeMMJSdfKgQaT2Ezoq4UhsOA/2BcXxpofx++KNrXNxXhUGUWCIGwph9wSznDKuofAGaz42bJum4o0M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748020488; c=relaxed/simple; bh=r2tIcGv/a54i+slS4UvLN7wMAS3AqDTQT3RLgno1eLc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=QnEqCMD2Vj2mor3vdWdNINOg5v0H91cZosHmQmA1tGmKiQnfg3ijBw4hAQP4LWzCUYxpER23FBNBUUQaONUWHCMmonWTCigETUILJSuhQ3De2gNQLyCxN7Nyb8y/5W1DrFpZXUYCSJuiACwcBRayewI4LDbmonJt3VSguPi07Ic= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=B3MLZdK6; arc=none smtp.client-ip=209.85.214.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="B3MLZdK6" Received: by mail-pl1-f175.google.com with SMTP id d9443c01a7336-2320d06b728so1015715ad.1 for ; Fri, 23 May 2025 10:14:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1748020484; x=1748625284; darn=vger.kernel.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=+ILKfp+PhHp1JJ4V01gttad8fE6fV6QpycD/TPbbAGI=; b=B3MLZdK6DX+eIzK9ceTuxGQs9JLt1FSQ5gcnIn8zFvJ8/pfM0/0e/F/UZe1knpETNx ht+NNLJID1CFt/p8dOB67Tc4+jvPe2Dr6u2HMlyPlQvMESXWNH1AdmRLy2NcrHyrknh/ d8bVrvPy0qUR2fQs3Lb1Yz/0zFEnF341ZSUtsmNx+QDTUrbxQGJ/X0gJZxdIhm6uDv8a 8ykbFnokaZDuYQrytttdzeD/fNRDpYyIF2oRk1lJSbxVqXq5QMWe9RNnLao0sJRwx/3J vqYn6y3vO8sXoT98LhVJT8rpbxHhMvzFgx6P2qu0FKtyLo4wj8m6uWLaj2XQxAhqw/T6 G23g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748020484; x=1748625284; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=+ILKfp+PhHp1JJ4V01gttad8fE6fV6QpycD/TPbbAGI=; b=L5svPasvP+EO1FNCqxZV7nafOsiKPz4qt0cRJRLcsfLlKc90Xk5+tpqUj2Sf7HUEVa U9Q7rxMlnWbqR4F0ypQCLeb7jHrfAWECv5vCBxZ4q6aszstypE8TlvIgNwm2Sp0DTlPU 2I2qE9vyvI7kAetPDlJo0T2j9RFPtPnbMfrTNR2OMcYLXlWTlOlkqoPbE1gzzh9Mq8sw O8Druutz/jTL3XeC1p1TCFhl8Zvzfs1uRPufd/RSPkYoc4x9pIpNsGOqKRMZysf9jwxU ux4Y+Tr/TVstV/IeCer6cXeCdKrAlucm+LvvG+2x+NCyfRB0LaVoj2NtT3xy2LxiZf07 +JMA== X-Forwarded-Encrypted: i=1; AJvYcCX7Z+xMm24U3aa5LlYr0r565lJnun9VAZETPe/aUllV+LSHdRl/FSq0bTi10ifMy1W+ZmsAkz+a5Pvc0mk=@vger.kernel.org X-Gm-Message-State: AOJu0YwTz88fbP4e69Aa+ffMYjKgubM5GoqZVQjA0tBInPF7P6hh09A7 8EYn6HqyMroxGjxd89ZPHlPDE6+rTE4Mq7fIkJ2bILxwxH8tX6Pr3dhd3UD9IpMTw9k= X-Gm-Gg: ASbGncvuHetuA6y/ojkDI/r7JLFZ+OEk/xeb+NCgx4xyuPhtWrWx3K7vaCWfvVt9MQv JRNmHXYoEUo+6HB8anWL/CLGGxpeRyenMfBuSL8u1Ll52Oh8C/Nw3d+qjzyyyVB2pNwoZ6qEUFX PnM5N5mflSQqkA4WiddPEEs8/WozTef84huATUxtH8lgz1hJ2twK3Jgk+h1lbJ4CGk8LvI+XaCi jWTDMQNIAMzi17rAiITo0wrf6cFLIR1lF/iJKk+9XCMMV5quYDyWhepuDoVtndlmrCVbZFvRBMg onS0fblGFFjWP0dNYk9RhgQ7cZoFQrBW8s+8M6NFkrwTny7C7Ekrz1Z7nc9kgg== X-Google-Smtp-Source: AGHT+IFYZp9eIXDMvWYA6hNO9vlZGOyZj5S0G8khsz4GfqLECIT4FzVceMBBxmyKMIqEgFnPJUUCxQ== X-Received: by 2002:a17:902:ea04:b0:233:fbb3:c5bc with SMTP id d9443c01a7336-23414f6d173mr2700345ad.19.1748020484256; Fri, 23 May 2025 10:14:44 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4ac91acsm126024045ad.46.2025.05.23.10.14.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 May 2025 10:14:43 -0700 (PDT) Date: Fri, 23 May 2025 10:14:41 -0700 From: Deepak Gupta To: Alexandre Ghiti Cc: Andy Chiu , Ben Dooks , Cyril Bur , palmer@dabbelt.com, aou@eecs.berkeley.edu, paul.walmsley@sifive.com, charlie@rivosinc.com, jrtc27@jrtc27.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, jszhang@kernel.org, syzbot+e74b94fe601ab9552d69@syzkaller.appspotmail.com Subject: Re: [PATCH v6 1/5] riscv: save the SR_SUM status over switches Message-ID: References: <20250410070526.3160847-1-cyrilbur@tenstorrent.com> <20250410070526.3160847-2-cyrilbur@tenstorrent.com> <54d63ebf-b66f-41d4-85b1-ec0fa3401333@ghiti.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <54d63ebf-b66f-41d4-85b1-ec0fa3401333@ghiti.fr> On Fri, May 23, 2025 at 02:22:21PM +0200, Alexandre Ghiti wrote: >Hi Andy, Deepak, > >On 5/23/25 00:43, Deepak Gupta wrote: >>On Fri, May 23, 2025 at 01:42:49AM +0800, Andy Chiu wrote: >>>On Thu, May 22, 2025 at 11:09 PM Deepak Gupta >>>wrote: >>>> >>>>On Thu, May 22, 2025 at 07:23:32AM +0100, Ben Dooks wrote: >>>>>On 20/05/2025 17:49, Deepak Gupta wrote: >>>>>>I did give this patch my RB and had planned to come back to it to see >>>>>>if it impacts cfi related patches. Thanks to alex for brinigng to my >>>>>>attention again. As it stands today, it doesn't impact cfi related >>>>>>changes but I've some concerns. >>>>>> >>>>>>Overall I do agree we should reduce number of SSTATUS accesses. >>>>>> >>>>>>Couple of questions on introducing new `sstatus` field (inline) >>>>>> >>>>>>On Tue, Apr 22, 2025 at 04:01:35PM -0700, Deepak Gupta wrote: >>>>>>>On Thu, Apr 10, 2025 at 07:05:22AM +0000, Cyril Bur wrote: >>>>>>>>From: Ben Dooks >>>>>>>> >>>>>>>>When threads/tasks are switched we need to ensure the old >>>>execution's >>>>>>>>SR_SUM state is saved and the new thread has the old SR_SUM state >>>>>>>>restored. >>>>>>>> >>>>>>>>The issue was seen under heavy load especially with the >>>>syz-stress tool >>>>>>>>running, with crashes as follows in schedule_tail: >>>>>>>> >>>>>>>>Unable to handle kernel access to user memory without >>>>uaccess routines >>>>>>>>at virtual address 000000002749f0d0 >>>>>>>>Oops [#1] >>>>>>>>Modules linked in: >>>>>>>>CPU: 1 PID: 4875 Comm: syz-executor.0 Not tainted >>>>>>>>5.12.0-rc2-syzkaller-00467-g0d7588ab9ef9 #0 >>>>>>>>Hardware name: riscv-virtio,qemu (DT) >>>>>>>>epc : schedule_tail+0x72/0xb2 kernel/sched/core.c:4264 >>>>>>>>ra : task_pid_vnr include/linux/sched.h:1421 [inline] >>>>>>>>ra : schedule_tail+0x70/0xb2 kernel/sched/core.c:4264 >>>>>>>>epc : ffffffe00008c8b0 ra : ffffffe00008c8ae sp : ffffffe025d17ec0 >>>>>>>>gp : ffffffe005d25378 tp : ffffffe00f0d0000 t0 : 0000000000000000 >>>>>>>>t1 : 0000000000000001 t2 : 00000000000f4240 s0 : ffffffe025d17ee0 >>>>>>>>s1 : 000000002749f0d0 a0 : 000000000000002a a1 : 0000000000000003 >>>>>>>>a2 : 1ffffffc0cfac500 a3 : ffffffe0000c80cc a4 : 5ae9db91c19bbe00 >>>>>>>>a5 : 0000000000000000 a6 : 0000000000f00000 a7 : ffffffe000082eba >>>>>>>>s2 : 0000000000040000 s3 : ffffffe00eef96c0 s4 : ffffffe022c77fe0 >>>>>>>>s5 : 0000000000004000 s6 : ffffffe067d74e00 s7 : ffffffe067d74850 >>>>>>>>s8 : ffffffe067d73e18 s9 : ffffffe067d74e00 s10: ffffffe00eef96e8 >>>>>>>>s11: 000000ae6cdf8368 t3 : 5ae9db91c19bbe00 t4 : ffffffc4043cafb2 >>>>>>>>t5 : ffffffc4043cafba t6 : 0000000000040000 >>>>>>>>status: 0000000000000120 badaddr: 000000002749f0d0 cause: >>>>>>>>000000000000000f >>>>>>>>Call Trace: >>>>>>>>[] schedule_tail+0x72/0xb2 >>>>kernel/sched/core.c:4264 >>>>>>>>[] ret_from_exception+0x0/0x14 >>>>>>>>Dumping ftrace buffer: >>>>>>>> (ftrace buffer empty) >>>>>>>>---[ end trace b5f8f9231dc87dda ]--- >>>>>>>> >>>>>>>>The issue comes from the put_user() in schedule_tail >>>>>>>>(kernel/sched/core.c) doing the following: >>>>>>>> >>>>>>>>asmlinkage __visible void schedule_tail(struct task_struct *prev) >>>>>>>>{ >>>>>>>>... >>>>>>>>      if (current->set_child_tid) >>>>>>>>              put_user(task_pid_vnr(current), >>>>current->set_child_tid); >>>>>>>>... >>>>>>>>} >>>>>>>> >>>>>>>>the put_user() macro causes the code sequence to come out as >>>>follows: >>>>>>>> >>>>>>>>1:    __enable_user_access() >>>>>>>>2:    reg = task_pid_vnr(current); >>>>>>>>3:    *current->set_child_tid = reg; >>>>>>>>4:    __disable_user_access() >>>>>>>> >>>>>>>>The problem is that we may have a sleeping function as >>>>argument which >>>>>>>>could clear SR_SUM causing the panic above. This was fixed by >>>>>>>>evaluating the argument of the put_user() macro outside the >>>>user-enabled >>>>>>>>section in commit 285a76bb2cf5 ("riscv: evaluate put_user() >>>>arg before >>>>>>>>enabling user access")" >>>>>>>> >>>>>>>>In order for riscv to take advantage of unsafe_get/put_XXX() >>>>macros and >>>>>>>>to avoid the same issue we had with put_user() and sleeping >>>>functions we >>>>>>>>must ensure code flow can go through switch_to() from within >>>>a region of >>>>>>>>code with SR_SUM enabled and come back with SR_SUM still >>>>enabled. This >>>>>>>>patch addresses the problem allowing future work to enable >>>>full use of >>>>>>>>unsafe_get/put_XXX() macros without needing to take a CSR >>>>bit flip cost >>>>>>>>on every access. Make switch_to() save and restore SR_SUM. >>>>>>>> >>>>>>>>Reported-by: syzbot+e74b94fe601ab9552d69@syzkaller.appspotmail.com >>>>>>>>Signed-off-by: Ben Dooks >>>>>>>>Signed-off-by: Cyril Bur >>>>>>>>--- >>>>>>>>arch/riscv/include/asm/processor.h | 1 + >>>>>>>>arch/riscv/kernel/asm-offsets.c    | 5 +++++ >>>>>>>>arch/riscv/kernel/entry.S          | 8 ++++++++ >>>>>>>>3 files changed, 14 insertions(+) >>>>>>>> >>>>>>>>diff --git a/arch/riscv/include/asm/processor.h >>>>>>>>b/arch/riscv/include/ asm/processor.h >>>>>>>>index 5f56eb9d114a..58fd11c89fe9 100644 >>>>>>>>--- a/arch/riscv/include/asm/processor.h >>>>>>>>+++ b/arch/riscv/include/asm/processor.h >>>>>>>>@@ -103,6 +103,7 @@ struct thread_struct { >>>>>>>>    struct __riscv_d_ext_state fstate; >>>>>>>>    unsigned long bad_cause; >>>>>>>>    unsigned long envcfg; >>>>>>>>+    unsigned long status; >>>>>> >>>>>>Do we really need a new member field in `thread_struct`. We >>>>already have >>>>>>`sstatus` in `pt_regs` which reflects overall execution environment >>>>>>situation >>>>>>for current thread. This gets saved and restored on trap entry >>>>and exit. >>>>>> >>>>>>If we put `status` in `thread_struct` it creates ambiguity in terms >>>>>>of which >>>>>>`status` to save to and pick from from future maintainibility >>>>>>purposes as the >>>>>>fields get introduced to this CSR. >>>>>> >>>>>>Why can't we access current trap frame's `sstatus` image in >>>>>>`__switch_to` to >>>>>>save and restore? >>>>>> >>>>>>Let me know if I am missing something obvious here. If there is a >>>>>>complication, >>>>>>I am missing here and we do end up using this member field, I would >>>>>>rename it >>>>>>to something like `status_kernel` to reflect that. So that future >>>>>>changes are >>>>>>cognizant of the fact that we have split `status`. One for kernel >>>>>>execution env >>>>>>per thread and one for controlling user execution env per thread. >>>>> >>>>>This is so long ago now I cannot remember if there was any sstatus in >>>>>the pt_regs field, >>>> >>>>FS/VS bits encode status of floating point and vector on >>>>per-thread basis. >>>>So `status` has been part of `pt_regs` for quite a while. >>>> >>>>> and if kernel threads have the same context as their >>>>>userland parts. >>>> >>>>I didn't mean kernel thread. What I meant was kernel execution >>>>environment >>>>per-thread. A userland thread does spend sometime in kernel and >>>>kernel does >>>>things on its behalf. One of those thing is touching user memory >>>>and that >>>>requires mucking with this CSR. So what I meant was are we >>>>splitting `status` >>>>on per-thread basis for their time spent in user and kernel. >>>> >>>>Getting back to original question-- >>>>As I said, each thread spends sometime in user or in kernel. >>>>`status` in >>>>`pt_regs` is saved on trap entry and restored on trap exit. In a sense, >>>>`status` field in `pt_regs` is reflecting execution status of >>>>the thread on per >>>>trap basis. Introducing `status` in `thread_struct` creates a >>>>confusion (if not >>>>for today, certainly for future) of which `status` to pick from >>>>when we are >>>>doing save/restore. >>> >>>I agree that it's a confusion. sstatus is already saved on pt_regs on >>>trap entries/return, adding another entry adds code complexity and >>>makes data inconsistent. But, perhaps we'd eventually need something >>>like this (I will explain why). Still, there might be a better >>>approach. >>> >>>Yes, we can always reflect pt_regs for sstatus. We all know that >>>pt_regs reflects sstatus at trap entry, and the pt_regs at scheduler >>>point refers to "user's" pt_regs whenever it first enters kernel >>>mode. Here >>>are reasons why SR_SUM here may or may not be properly tracked. First, >>>if this is a trap introduced context switch (such as interrupting in a >>>preemptible context after we manually enable user access in put_user), >>>then SR_SUM is saved somewhere in the kernel stack, and is not >>>reference-able with task_pt_reg during context switch. But we are safe >>>because the trap exit asm would help us restore the correct SR_SUM >>>back. However, if this is a self-initiating context switch (calling >>>into schedule()), then SR_SUM is not saved anywhere, and possibly >>>causing this error. >>> >>>Preemptible Vector in the kernel mode also had this problem where a >>>self-initiating context switch loses the track of sstatus.vs. The way >>>I managed it is to track the VS bit at context switch time. However, >>>this bug shows that people are repeatedly facing the problem, and >>>maybe it suggests that we'd need a better way of managing sstatus >>>across context switches. Given the complex nature of this register, >>>which also touches the interrupt enable status, I don't think naively >>>saving/restoring the entire register is the way to go. Maybe the >>>variable deserves a more specific naming and documentation. And if >>>we'd need a centralized place for managing these statuses, then it >>>also has to take care of sstatus.VS. > > >Andy, thanks for the precise explanation of the problem :) > >So it took me some time but here are my thoughts on this. We should >treat pt_regs and thread_struct differently as they do not represent >the same thing: >- pt_regs represents the context of a thread when it takes a trap >- thread_struct represents a "kernel-induced" (or a "in-kernel") >context not caused by traps Exactly they represent different context of execution. Trap represents a non-linear control flow change and thus a fresh start of execution control flow into kernel while `kernel-induced` one's are again non-linear but fully a kernel/software construct. A fresh trapped execution context shouldn't have SUM set which is how it is currently in kernel. This bit gets cleared in trap entry and `sstatus` gets saved in `pt_regs` (including SR_IE) so that it could be restored whenever `sret` happens. The problem we'are seeing here is two fold-- 1) We don't want to set and clear when we are accessing array/string for each word. This is software problem and this entire series is addressing it. 2) To avoid first problem we are optimizing the access to CSR by setting it once and clearing it once. But now we don't want to loose this bit if there were: a) trap in between b) kernel induced schedule out c) a) followed by b) d) a) followed by another a) e) nested traps If a) occurs, we are definitley loosing the bit as per current code. If b) happens then also the same situation. Saving it in `thread_struct` only addresses `b`. And not `a`, `c`, `d` and `e`. IMHO `e` is far-fetched situation but I believe `a`, `b`, `c` and `d` happen during normal runtime of kernel. So it all depends on nesting level of traps supported by riscv kernel. Illustraing `c + d` example, if kernel can take 2 nested level of traps with first trap context having had the SUM bit set, but the second trap had it clear and now comes the switch out of this thread, at this point if it were saved in `thread_struct` SUM would be lost for the first trap. Later when the thread gets switched in again, you would go in 2nd trap context without SUM (because `thread_context` didnt had it saved), which is fine. Although when 2nd trap context eventually performs `sret`, it will go back to first trap context where SUM was expected to be set because it touching a user memory. A good example would be a syscall, so that's the first trap. SUM bit is set, touched user memory and took a trap (page fault). Now code is in second trap which should clear the SUM bit. Somewhere in memory manager stack, thread is scheduled out and now `sstatus` is saved in `thread_struct`. This is only serving current trap context needs and not the one where `SUM` needed to be set. We can support such nesting only by ensuring below On trap entry do - save `status` in `pt_regs` or some other FILO data structure - clear SUM (and other bits needed to be cleared) On trap return do - reload `status` from `pt_regs` or some FILO data structure Quite analogous to what we do for SR_IE as well. > >That's why I don't really like Deepak's proposal below as it mixes >both and I find it tricky. > >I can't find a situation where saving/restoring the entire sstatus at >context-switch is a problem though, does anyone have such thing in >mind? > >Finally I understand that having another copy of sstatus in >thread_struct is not intuitive and we should, either explain why or >only store the SUM bit (like for sstatus.VS). > >Please continue the discussion as we need to find a solution that >pleases everyone soon :) > >Thanks all for jumping in, > >Alex > > >> >> >>IMHO, the problem we are trying to solve in this patch is easily >>solvable in >>below manner. >> >> >>diff --git a/arch/riscv/include/asm/switch_to.h >>b/arch/riscv/include/asm/switch_to.h >>index 0e71eb82f920..499d00a6fb67 100644 >>--- a/arch/riscv/include/asm/switch_to.h >>+++ b/arch/riscv/include/asm/switch_to.h >>@@ -58,6 +58,20 @@ static inline void __switch_to_fpu(struct >>task_struct *prev, >>        fstate_restore(next, task_pt_regs(next)); >> } >> >>+static inline void __switch_to_status(struct task_struct *prev, >>+                                  struct task_struct *next) >>+{ >>+       struct pt_regs *regs; >>+ >>+       /* save status */ >>+       regs = task_pt_regs(prev); >>+       regs->status = csr_read(CSR_STATUS); >>+ >>+       /* restore status */ >>+       regs = task_pt_regs(next); >>+       csr_write(CSR_STATUS, regs->status); >>+} >>+ >> static __always_inline bool has_fpu(void) >> { >>        return riscv_has_extension_likely(RISCV_ISA_EXT_f) || >>@@ -115,6 +129,7 @@ do >>{                                                        \ >>        struct task_struct *__prev = (prev);            \ >>        struct task_struct *__next = (next);            \ >>        __set_prev_cpu(__prev->thread);                 \ >>+       __switch_to_status(__prev, __next)              \ >>        if (has_fpu())                                  \ >>                __switch_to_fpu(__prev, __next);        \ >>        if (has_vector() || has_xtheadvector())         \ >>diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S >>index 8d25837a9384..a3b98c1be055 100644 >>--- a/arch/riscv/kernel/entry.S >>+++ b/arch/riscv/kernel/entry.S >>@@ -162,17 +162,8 @@ SYM_CODE_START(handle_exception) >>        REG_S x5,  PT_T0(sp) >>        save_from_x6_to_x31 >> >>-       /* >>-        * Disable user-mode memory access as it should only be set >>in the >>-        * actual user copy routines. >>-        * >>-        * Disable the FPU/Vector to detect illegal usage of >>floating point >>-        * or vector in kernel space. >>-        */ >>-       li t0, SR_SUM | SR_FS_VS | SR_ELP >>- >>        REG_L s0, TASK_TI_USER_SP(tp) >>-       csrrc s1, CSR_STATUS, t0 >>+       csrr s1, CSR_STATUS >>        save_userssp s2, s1 >>        csrr s2, CSR_EPC >>        csrr s3, CSR_TVAL >>@@ -185,6 +176,16 @@ SYM_CODE_START(handle_exception) >>        REG_S s4, PT_CAUSE(sp) >>        REG_S s5, PT_TP(sp) >> >>+       /* >>+        * It is fresh trap entry. Disable user-mode memory access >>as it should only be set in the >>+        * actual user copy routines. >>+        * >>+        * Disable the FPU/Vector to detect illegal usage of >>floating point >>+        * or vector in kernel space. >>+        */ >>+       li t0, SR_SUM | SR_FS_VS | SR_ELP >>+       csrrc s1, CSR_STATUS, t0 >>+ >>        /* >>         * Set the scratch register to 0, so that if a recursive >>exception >>         * occurs, the exception vector knows it came from the kernel >> >> >> >>During the time spent in kernel if sets SUM bit in status then, above >>`__switch_to_status` will ensure that `status` will get saved for current >>thread and restored for next thread. >> >>Furthermore, current trap entry code clears FS/VS/SUM (for right >>reasons). It >>represents non-linear change of control flow and thus whatever will >>execute next >>shouldn't need SUM/FS/VS unless it wants to set it). This patch slightly >>modifies the flow by first saving the `status` on trap frame (thus >>if previous >>trap frame had SUM=1, it will be saved and restored). And then it >>unconditionally clears the SUM/FS/VS to ensure that this new trap >>context runs >>without needing SUM=1. This ensures nesting of trap frames without >>diluting >>security properties of SUM. >> >>> >>>Thanks, >>>Andy >>> >>> >>> >>> >>>> >>>>So my first question was why not to use `status` in `pt_regs`. >>>>It is granular >>>>as it can get (it is available per thread context per trap basis). >>>> >>>> >>>>I did ask Alex as well. I'll ping him again. >>>> >>>>> >>>>>Does anyone else have any comment on this? >>>>> >>>>>> >>>>>>>>    u32 riscv_v_flags; >>>>>>>>    u32 vstate_ctrl; >>>>>>>>    struct __riscv_v_ext_state vstate; >>>>>>>>diff --git a/arch/riscv/kernel/asm-offsets.c >>>>>>>>b/arch/riscv/kernel/asm- offsets.c >>>>>>>>index 16490755304e..969c65b1fe41 100644 >>>>>>>>--- a/arch/riscv/kernel/asm-offsets.c >>>>>>>>+++ b/arch/riscv/kernel/asm-offsets.c >>>>>>>>@@ -34,6 +34,7 @@ void asm_offsets(void) >>>>>>>>    OFFSET(TASK_THREAD_S9, task_struct, thread.s[9]); >>>>>>>>    OFFSET(TASK_THREAD_S10, task_struct, thread.s[10]); >>>>>>>>    OFFSET(TASK_THREAD_S11, task_struct, thread.s[11]); >>>>>> >>>>>>_______________________________________________ >>>>>>linux-riscv mailing list >>>>>>linux-riscv@lists.infradead.org >>>>>>http://lists.infradead.org/mailman/listinfo/linux-riscv >>>>>> >>>>> >>>>> >>>>>-- >>>>>Ben Dooks http://www.codethink.co.uk/ >>>>>Senior Engineer                                Codethink - >>>>Providing Genius >>>>> >>>>>https://www.codethink.co.uk/privacy.html >>>> >>>>_______________________________________________ >>>>linux-riscv mailing list >>>>linux-riscv@lists.infradead.org >>>>http://lists.infradead.org/mailman/listinfo/linux-riscv >> >>_______________________________________________ >>linux-riscv mailing list >>linux-riscv@lists.infradead.org >>http://lists.infradead.org/mailman/listinfo/linux-riscv