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Fri, 23 May 2025 11:36:30 -0700 (PDT) Received: from ghost ([2601:647:6700:64d0:bb2c:c7d9:9014:13ab]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4ed897asm127271765ad.250.2025.05.23.11.36.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 May 2025 11:36:30 -0700 (PDT) Date: Fri, 23 May 2025 11:36:28 -0700 From: Charlie Jenkins To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland , Andrew Jones , Deepak Gupta Subject: Re: [PATCH v8 08/14] riscv: misaligned: declare misaligned_access_speed under CONFIG_RISCV_MISALIGNED Message-ID: References: <20250523101932.1594077-1-cleger@rivosinc.com> <20250523101932.1594077-9-cleger@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250523101932.1594077-9-cleger@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250523_113631_842658_2AF91638 X-CRM114-Status: GOOD ( 17.60 ) X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+kvm-riscv=archiver.kernel.org@lists.infradead.org On Fri, May 23, 2025 at 12:19:25PM +0200, Cl=E9ment L=E9ger wrote: > While misaligned_access_speed was defined in a file compile with > CONFIG_RISCV_MISALIGNED, its definition was under > CONFIG_RISCV_SCALAR_MISALIGNED. This resulted in compilation problems > when using it in a file compiled with CONFIG_RISCV_MISALIGNED. > = > Move the declaration under CONFIG_RISCV_MISALIGNED so that it can be > used unconditionnally when compiled with that config and remove the check > for that variable in traps_misaligned.c. > = > Signed-off-by: Cl=E9ment L=E9ger Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins > --- > arch/riscv/include/asm/cpufeature.h | 5 ++++- > arch/riscv/kernel/traps_misaligned.c | 2 -- > 2 files changed, 4 insertions(+), 3 deletions(-) > = > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm= /cpufeature.h > index dbe5970d4fe6..2bfa4ef383ed 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -72,7 +72,6 @@ int cpu_online_unaligned_access_init(unsigned int cpu); > #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) > void unaligned_emulation_finish(void); > bool unaligned_ctl_available(void); > -DECLARE_PER_CPU(long, misaligned_access_speed); > #else > static inline bool unaligned_ctl_available(void) > { > @@ -80,6 +79,10 @@ static inline bool unaligned_ctl_available(void) > } > #endif > = > +#if defined(CONFIG_RISCV_MISALIGNED) > +DECLARE_PER_CPU(long, misaligned_access_speed); > +#endif > + > bool __init check_vector_unaligned_access_emulated_all_cpus(void); > #if defined(CONFIG_RISCV_VECTOR_MISALIGNED) > void check_vector_unaligned_access_emulated(struct work_struct *work __a= lways_unused); > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/tra= ps_misaligned.c > index 34b4a4e9dfca..f1b2af515592 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -369,9 +369,7 @@ static int handle_scalar_misaligned_load(struct pt_re= gs *regs) > = > perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); > = > -#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS > *this_cpu_ptr(&misaligned_access_speed) =3D RISCV_HWPROBE_MISALIGNED_SC= ALAR_EMULATED; > -#endif > = > if (!unaligned_enabled) > return -1; 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Fri, 23 May 2025 11:36:30 -0700 (PDT) Received: from ghost ([2601:647:6700:64d0:bb2c:c7d9:9014:13ab]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4ed897asm127271765ad.250.2025.05.23.11.36.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 May 2025 11:36:30 -0700 (PDT) Date: Fri, 23 May 2025 11:36:28 -0700 From: Charlie Jenkins To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland , Andrew Jones , Deepak Gupta Subject: Re: [PATCH v8 08/14] riscv: misaligned: declare misaligned_access_speed under CONFIG_RISCV_MISALIGNED Message-ID: References: <20250523101932.1594077-1-cleger@rivosinc.com> <20250523101932.1594077-9-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250523101932.1594077-9-cleger@rivosinc.com> On Fri, May 23, 2025 at 12:19:25PM +0200, Clément Léger wrote: > While misaligned_access_speed was defined in a file compile with > CONFIG_RISCV_MISALIGNED, its definition was under > CONFIG_RISCV_SCALAR_MISALIGNED. This resulted in compilation problems > when using it in a file compiled with CONFIG_RISCV_MISALIGNED. > > Move the declaration under CONFIG_RISCV_MISALIGNED so that it can be > used unconditionnally when compiled with that config and remove the check > for that variable in traps_misaligned.c. > > Signed-off-by: Clément Léger Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins > --- > arch/riscv/include/asm/cpufeature.h | 5 ++++- > arch/riscv/kernel/traps_misaligned.c | 2 -- > 2 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h > index dbe5970d4fe6..2bfa4ef383ed 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -72,7 +72,6 @@ int cpu_online_unaligned_access_init(unsigned int cpu); > #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) > void unaligned_emulation_finish(void); > bool unaligned_ctl_available(void); > -DECLARE_PER_CPU(long, misaligned_access_speed); > #else > static inline bool unaligned_ctl_available(void) > { > @@ -80,6 +79,10 @@ static inline bool unaligned_ctl_available(void) > } > #endif > > +#if defined(CONFIG_RISCV_MISALIGNED) > +DECLARE_PER_CPU(long, misaligned_access_speed); > +#endif > + > bool __init check_vector_unaligned_access_emulated_all_cpus(void); > #if defined(CONFIG_RISCV_VECTOR_MISALIGNED) > void check_vector_unaligned_access_emulated(struct work_struct *work __always_unused); > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c > index 34b4a4e9dfca..f1b2af515592 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -369,9 +369,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) > > perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); > > -#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS > *this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED; > -#endif > > if (!unaligned_enabled) > return -1; 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Fri, 23 May 2025 11:36:30 -0700 (PDT) Received: from ghost ([2601:647:6700:64d0:bb2c:c7d9:9014:13ab]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4ed897asm127271765ad.250.2025.05.23.11.36.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 May 2025 11:36:30 -0700 (PDT) Date: Fri, 23 May 2025 11:36:28 -0700 From: Charlie Jenkins To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland , Andrew Jones , Deepak Gupta Subject: Re: [PATCH v8 08/14] riscv: misaligned: declare misaligned_access_speed under CONFIG_RISCV_MISALIGNED Message-ID: References: <20250523101932.1594077-1-cleger@rivosinc.com> <20250523101932.1594077-9-cleger@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250523101932.1594077-9-cleger@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250523_113631_845140_0ACEE9D4 X-CRM114-Status: GOOD ( 17.60 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, May 23, 2025 at 12:19:25PM +0200, Cl=E9ment L=E9ger wrote: > While misaligned_access_speed was defined in a file compile with > CONFIG_RISCV_MISALIGNED, its definition was under > CONFIG_RISCV_SCALAR_MISALIGNED. This resulted in compilation problems > when using it in a file compiled with CONFIG_RISCV_MISALIGNED. > = > Move the declaration under CONFIG_RISCV_MISALIGNED so that it can be > used unconditionnally when compiled with that config and remove the check > for that variable in traps_misaligned.c. > = > Signed-off-by: Cl=E9ment L=E9ger Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins > --- > arch/riscv/include/asm/cpufeature.h | 5 ++++- > arch/riscv/kernel/traps_misaligned.c | 2 -- > 2 files changed, 4 insertions(+), 3 deletions(-) > = > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm= /cpufeature.h > index dbe5970d4fe6..2bfa4ef383ed 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -72,7 +72,6 @@ int cpu_online_unaligned_access_init(unsigned int cpu); > #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) > void unaligned_emulation_finish(void); > bool unaligned_ctl_available(void); > -DECLARE_PER_CPU(long, misaligned_access_speed); > #else > static inline bool unaligned_ctl_available(void) > { > @@ -80,6 +79,10 @@ static inline bool unaligned_ctl_available(void) > } > #endif > = > +#if defined(CONFIG_RISCV_MISALIGNED) > +DECLARE_PER_CPU(long, misaligned_access_speed); > +#endif > + > bool __init check_vector_unaligned_access_emulated_all_cpus(void); > #if defined(CONFIG_RISCV_VECTOR_MISALIGNED) > void check_vector_unaligned_access_emulated(struct work_struct *work __a= lways_unused); > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/tra= ps_misaligned.c > index 34b4a4e9dfca..f1b2af515592 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -369,9 +369,7 @@ static int handle_scalar_misaligned_load(struct pt_re= gs *regs) > = > perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); > = > -#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS > *this_cpu_ptr(&misaligned_access_speed) =3D RISCV_HWPROBE_MISALIGNED_SC= ALAR_EMULATED; > -#endif > = > if (!unaligned_enabled) > return -1; > -- = > 2.49.0 > = _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv