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Fri, 23 May 2025 11:39:04 -0700 (PDT) Received: from ghost ([2601:647:6700:64d0:bb2c:c7d9:9014:13ab]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4ed2508sm127432885ad.221.2025.05.23.11.39.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 May 2025 11:39:04 -0700 (PDT) Date: Fri, 23 May 2025 11:39:02 -0700 From: Charlie Jenkins To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland , Andrew Jones , Deepak Gupta Subject: Re: [PATCH v8 10/14] riscv: misaligned: add a function to check misalign trap delegability Message-ID: References: <20250523101932.1594077-1-cleger@rivosinc.com> <20250523101932.1594077-11-cleger@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250523101932.1594077-11-cleger@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250523_113905_947581_D03EA339 X-CRM114-Status: GOOD ( 18.92 ) X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+kvm-riscv=archiver.kernel.org@lists.infradead.org On Fri, May 23, 2025 at 12:19:27PM +0200, Cl=E9ment L=E9ger wrote: > Checking for the delegability of the misaligned access trap is needed > for the KVM FWFT extension implementation. Add a function to get the > delegability of the misaligned trap exception. > = > Signed-off-by: Cl=E9ment L=E9ger > Reviewed-by: Andrew Jones Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins > --- > arch/riscv/include/asm/cpufeature.h | 6 ++++++ > arch/riscv/kernel/traps_misaligned.c | 17 +++++++++++++++-- > 2 files changed, 21 insertions(+), 2 deletions(-) > = > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm= /cpufeature.h > index 2bfa4ef383ed..fbd0e4306c93 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -81,6 +81,12 @@ static inline bool unaligned_ctl_available(void) > = > #if defined(CONFIG_RISCV_MISALIGNED) > DECLARE_PER_CPU(long, misaligned_access_speed); > +bool misaligned_traps_can_delegate(void); > +#else > +static inline bool misaligned_traps_can_delegate(void) > +{ > + return false; > +} > #endif > = > bool __init check_vector_unaligned_access_emulated_all_cpus(void); > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/tra= ps_misaligned.c > index 7ecaa8103fe7..93043924fe6c 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -724,10 +724,10 @@ static int cpu_online_check_unaligned_access_emulat= ed(unsigned int cpu) > } > #endif > = > -#ifdef CONFIG_RISCV_SBI > - > static bool misaligned_traps_delegated; > = > +#ifdef CONFIG_RISCV_SBI > + > static int cpu_online_sbi_unaligned_setup(unsigned int cpu) > { > if (sbi_fwft_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0) && > @@ -763,6 +763,7 @@ static int cpu_online_sbi_unaligned_setup(unsigned in= t cpu __always_unused) > { > return 0; > } > + > #endif > = > int cpu_online_unaligned_access_init(unsigned int cpu) > @@ -775,3 +776,15 @@ int cpu_online_unaligned_access_init(unsigned int cp= u) > = > return cpu_online_check_unaligned_access_emulated(cpu); > } > + > +bool misaligned_traps_can_delegate(void) > +{ > + /* > + * Either we successfully requested misaligned traps delegation for all > + * CPUs, or the SBI does not implement the FWFT extension but delegated > + * the exception by default. > + */ > + return misaligned_traps_delegated || > + all_cpus_unaligned_scalar_access_emulated(); > +} > +EXPORT_SYMBOL_GPL(misaligned_traps_can_delegate); > -- = > 2.49.0 > = -- = kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BBF747F4A for ; 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Fri, 23 May 2025 11:39:04 -0700 (PDT) Received: from ghost ([2601:647:6700:64d0:bb2c:c7d9:9014:13ab]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4ed2508sm127432885ad.221.2025.05.23.11.39.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 May 2025 11:39:04 -0700 (PDT) Date: Fri, 23 May 2025 11:39:02 -0700 From: Charlie Jenkins To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland , Andrew Jones , Deepak Gupta Subject: Re: [PATCH v8 10/14] riscv: misaligned: add a function to check misalign trap delegability Message-ID: References: <20250523101932.1594077-1-cleger@rivosinc.com> <20250523101932.1594077-11-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250523101932.1594077-11-cleger@rivosinc.com> On Fri, May 23, 2025 at 12:19:27PM +0200, Clément Léger wrote: > Checking for the delegability of the misaligned access trap is needed > for the KVM FWFT extension implementation. Add a function to get the > delegability of the misaligned trap exception. > > Signed-off-by: Clément Léger > Reviewed-by: Andrew Jones Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins > --- > arch/riscv/include/asm/cpufeature.h | 6 ++++++ > arch/riscv/kernel/traps_misaligned.c | 17 +++++++++++++++-- > 2 files changed, 21 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h > index 2bfa4ef383ed..fbd0e4306c93 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -81,6 +81,12 @@ static inline bool unaligned_ctl_available(void) > > #if defined(CONFIG_RISCV_MISALIGNED) > DECLARE_PER_CPU(long, misaligned_access_speed); > +bool misaligned_traps_can_delegate(void); > +#else > +static inline bool misaligned_traps_can_delegate(void) > +{ > + return false; > +} > #endif > > bool __init check_vector_unaligned_access_emulated_all_cpus(void); > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c > index 7ecaa8103fe7..93043924fe6c 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -724,10 +724,10 @@ static int cpu_online_check_unaligned_access_emulated(unsigned int cpu) > } > #endif > > -#ifdef CONFIG_RISCV_SBI > - > static bool misaligned_traps_delegated; > > +#ifdef CONFIG_RISCV_SBI > + > static int cpu_online_sbi_unaligned_setup(unsigned int cpu) > { > if (sbi_fwft_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0) && > @@ -763,6 +763,7 @@ static int cpu_online_sbi_unaligned_setup(unsigned int cpu __always_unused) > { > return 0; > } > + > #endif > > int cpu_online_unaligned_access_init(unsigned int cpu) > @@ -775,3 +776,15 @@ int cpu_online_unaligned_access_init(unsigned int cpu) > > return cpu_online_check_unaligned_access_emulated(cpu); > } > + > +bool misaligned_traps_can_delegate(void) > +{ > + /* > + * Either we successfully requested misaligned traps delegation for all > + * CPUs, or the SBI does not implement the FWFT extension but delegated > + * the exception by default. > + */ > + return misaligned_traps_delegated || > + all_cpus_unaligned_scalar_access_emulated(); > +} > +EXPORT_SYMBOL_GPL(misaligned_traps_can_delegate); > -- > 2.49.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E60DFC54ED1 for ; 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Fri, 23 May 2025 11:39:04 -0700 (PDT) Received: from ghost ([2601:647:6700:64d0:bb2c:c7d9:9014:13ab]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-231d4ed2508sm127432885ad.221.2025.05.23.11.39.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 May 2025 11:39:04 -0700 (PDT) Date: Fri, 23 May 2025 11:39:02 -0700 From: Charlie Jenkins To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland , Andrew Jones , Deepak Gupta Subject: Re: [PATCH v8 10/14] riscv: misaligned: add a function to check misalign trap delegability Message-ID: References: <20250523101932.1594077-1-cleger@rivosinc.com> <20250523101932.1594077-11-cleger@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250523101932.1594077-11-cleger@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250523_113905_946991_055FA0FB X-CRM114-Status: GOOD ( 18.92 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, May 23, 2025 at 12:19:27PM +0200, Cl=E9ment L=E9ger wrote: > Checking for the delegability of the misaligned access trap is needed > for the KVM FWFT extension implementation. Add a function to get the > delegability of the misaligned trap exception. > = > Signed-off-by: Cl=E9ment L=E9ger > Reviewed-by: Andrew Jones Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins > --- > arch/riscv/include/asm/cpufeature.h | 6 ++++++ > arch/riscv/kernel/traps_misaligned.c | 17 +++++++++++++++-- > 2 files changed, 21 insertions(+), 2 deletions(-) > = > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm= /cpufeature.h > index 2bfa4ef383ed..fbd0e4306c93 100644 > --- a/arch/riscv/include/asm/cpufeature.h > +++ b/arch/riscv/include/asm/cpufeature.h > @@ -81,6 +81,12 @@ static inline bool unaligned_ctl_available(void) > = > #if defined(CONFIG_RISCV_MISALIGNED) > DECLARE_PER_CPU(long, misaligned_access_speed); > +bool misaligned_traps_can_delegate(void); > +#else > +static inline bool misaligned_traps_can_delegate(void) > +{ > + return false; > +} > #endif > = > bool __init check_vector_unaligned_access_emulated_all_cpus(void); > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/tra= ps_misaligned.c > index 7ecaa8103fe7..93043924fe6c 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -724,10 +724,10 @@ static int cpu_online_check_unaligned_access_emulat= ed(unsigned int cpu) > } > #endif > = > -#ifdef CONFIG_RISCV_SBI > - > static bool misaligned_traps_delegated; > = > +#ifdef CONFIG_RISCV_SBI > + > static int cpu_online_sbi_unaligned_setup(unsigned int cpu) > { > if (sbi_fwft_set(SBI_FWFT_MISALIGNED_EXC_DELEG, 1, 0) && > @@ -763,6 +763,7 @@ static int cpu_online_sbi_unaligned_setup(unsigned in= t cpu __always_unused) > { > return 0; > } > + > #endif > = > int cpu_online_unaligned_access_init(unsigned int cpu) > @@ -775,3 +776,15 @@ int cpu_online_unaligned_access_init(unsigned int cp= u) > = > return cpu_online_check_unaligned_access_emulated(cpu); > } > + > +bool misaligned_traps_can_delegate(void) > +{ > + /* > + * Either we successfully requested misaligned traps delegation for all > + * CPUs, or the SBI does not implement the FWFT extension but delegated > + * the exception by default. > + */ > + return misaligned_traps_delegated || > + all_cpus_unaligned_scalar_access_emulated(); > +} > +EXPORT_SYMBOL_GPL(misaligned_traps_can_delegate); > -- = > 2.49.0 > = _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv