From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 04E43C5B542 for ; Tue, 27 May 2025 20:59:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3xaxL1z9jAPAXi+HQJYz65Kop+G0gBM5OckJyMoVDjQ=; b=sVb/9XJzYPS8l2BTbnDpmak/Mv eMEY9fntamKGaoezHKTcsASLoHCUeJ0f2P9+NT+sHA+kD3Ms2AtO9jPRlbd6LxlaZXLUA3/yzILSf 81WWfnhEQsFtgR4+LJbAqq3rwPuCtwXHB2S5b8+YaOirMy3jzg40UKI2gFYaJ7dCCW6wsnmRnbCJ0 +UDUYxADhKXoDSipDdXkKrEj8QzSF/hJ5F+hZHdTUHWyT+gyLA112XGT4VgsBfU5S11zX8HhBGbFJ mo+R3h516oioKDuZKo9QvbvQiErAH26+FANdt4x9sLy+8g7cutjUypeWicSTxE9nTbV6szycW5phn HfDVQcdQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uK1Nu-0000000BYF9-3N9q; Tue, 27 May 2025 20:58:54 +0000 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uK1NP-0000000BYCI-44gL for linux-riscv@lists.infradead.org; Tue, 27 May 2025 20:58:25 +0000 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-72d3b48d2ffso2932667b3a.2 for ; Tue, 27 May 2025 13:58:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1748379503; x=1748984303; darn=lists.infradead.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=aNdKSRE+7GllioeuKKKCmHh0OzVPY+Ey8A+JicvvVpc=; b=al/u+2FRAvOahRZi9k4EmwaWk9RXAA83OWeS19LfYw5iqF5FsEgJZSWCADtof9WBb9 /IJ4nJZRCorG+KofU9MAtOyvIa0/0CxRiw88BuqIRZhnXm+oRmkFVuaDYCANAbp/vjhH RwbR53ActJkREn+mx0sTS3zkjGcQ6ETxmAmMOrMMfJfvTOoMKiWmp2H0IwdtVylslde2 RNVicApYVp5lpsaxtpV+gzeqwMj2dmqFVlZn396KJ4M6nOD1qnaAXUyGxHpHT/oyLbuK rOHWVNjWxkDXhXo87x3VwGgTPWvkS34ZTqzlLGcaGxbzW7JFzeFd72VqCwKS+jEhhvcy uZ+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748379503; x=1748984303; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=aNdKSRE+7GllioeuKKKCmHh0OzVPY+Ey8A+JicvvVpc=; b=N+K0DDQYHMcUYzPaQem5vPrGBh8vVGGgwsUbNfuEhD5BP4T0K9hLQyPcWDLlqtaMWZ Cv1a2PIFh6jXf/iUpHFXChSEbiYGXbULjPo4a6B39Gs0Y6zmKJDhmXmINor3v8SD+ogM TAhs/c5SKjPamNnWUZ5QycEnCfDkahsaha6m76gDOyJCGkjsz6Y67Ety/zNCVvllQwjz 0NpwdAVYVv1U/KYJhcfFi4YJ76QmLzzQ+409p2y4WES7koW+zlNZAWq8Ek8sBLnIZ8xL g+c8bghpTDnOWe58i5iFRTr5knfbw3kbo4utk3NGYxFmTc+T6+ZwQRxONmYhI0mD3v47 FEIA== X-Forwarded-Encrypted: i=1; AJvYcCW51R3tjQM9C3pqyctbiV/P7hltWwhjAGBazgkkM2zKqqhbv1H9ZCK3/Bqd2Z/FCb+9nIyk+XtdF/UzoQ==@lists.infradead.org X-Gm-Message-State: AOJu0YzouCPMS8caJjayXjukAyEMmJ8fYRURhfne+xmK4k7m5FhcDRT7 it/DnZw5Nk5jqgZbga+j7EM/sRolLBJFlnBaZBniU6g+IpddfQ8RNQXUJA27pPhZuBI= X-Gm-Gg: ASbGncu+oVSuU4Z0I9SOvo3T1mSFZXVkWpe4RJ8ryHzwr0Qyb4ogFgYB2xvz7B0qaeG h+TXUDxcGyKXjI4xfwan9JcPT5Cs0+uSez1Ry2BW9TE7Tk9Dc0EXgQ//2gQCUn9lbQXbRR5kmaH hgiDCji1f7LZiJFinwQOncAGR6DwKsaWPutYdHu9l19K1Zp24Zsx3bSyemapBbVsOWIDwcWF79i +c/Kr3mhmk1rSZKJCwKKuZx/PglLuxKj5dNvSsde9oO5rQFw2YZFVhikC7GFXzZlXCN03NH8Ell yC5qWY03Oa0pc0JxSAOiAZS4R27to/gw6meR57hZgBrRG51DuvgVnpOiOYGreg== X-Google-Smtp-Source: AGHT+IF80NTZE/eApE9Z4200qK9MpmEpuFOgm2Uyz77PLVPr0kED6gBP29OsakUyqzggLqC0QjIHww== X-Received: by 2002:a05:6a20:7d9b:b0:215:f26f:90e9 with SMTP id adf61e73a8af0-2188c299141mr22152343637.22.1748379502952; Tue, 27 May 2025 13:58:22 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74668301bacsm12016b3a.169.2025.05.27.13.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 May 2025 13:58:22 -0700 (PDT) Date: Tue, 27 May 2025 13:58:20 -0700 From: Deepak Gupta To: Andy Chiu Cc: Alexandre Ghiti , Ben Dooks , Cyril Bur , palmer@dabbelt.com, aou@eecs.berkeley.edu, paul.walmsley@sifive.com, charlie@rivosinc.com, jrtc27@jrtc27.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, jszhang@kernel.org, syzbot+e74b94fe601ab9552d69@syzkaller.appspotmail.com Subject: Re: [PATCH v6 1/5] riscv: save the SR_SUM status over switches Message-ID: References: <20250410070526.3160847-2-cyrilbur@tenstorrent.com> <54d63ebf-b66f-41d4-85b1-ec0fa3401333@ghiti.fr> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250527_135824_309213_37B25585 X-CRM114-Status: GOOD ( 39.16 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org T24gU2F0LCBNYXkgMjQsIDIwMjUgYXQgMDY6MDA6MDBQTSArMDgwMCwgQW5keSBDaGl1IHdyb3Rl Ogo+T24gU2F0LCBNYXkgMjQsIDIwMjUgYXQgMToxNOKAr0FNIERlZXBhayBHdXB0YSA8ZGVidWdA cml2b3NpbmMuY29tPiB3cm90ZToKPj4KPj4gT24gRnJpLCBNYXkgMjMsIDIwMjUgYXQgMDI6MjI6 MjFQTSArMDIwMCwgQWxleGFuZHJlIEdoaXRpIHdyb3RlOgo+PiA+SGkgQW5keSwgRGVlcGFrLAo+ PiA+Cj4+ID5PbiA1LzIzLzI1IDAwOjQzLCBEZWVwYWsgR3VwdGEgd3JvdGU6Cj4+ID4+T24gRnJp LCBNYXkgMjMsIDIwMjUgYXQgMDE6NDI6NDlBTSArMDgwMCwgQW5keSBDaGl1IHdyb3RlOgo+PiA+ Pj5PbiBUaHUsIE1heSAyMiwgMjAyNSBhdCAxMTowOeKAr1BNIERlZXBhayBHdXB0YSA8ZGVidWdA cml2b3NpbmMuY29tPgo+PiA+Pj53cm90ZToKPj4gPj4+Pgo+PiA+Pj4+T24gVGh1LCBNYXkgMjIs IDIwMjUgYXQgMDc6MjM6MzJBTSArMDEwMCwgQmVuIERvb2tzIHdyb3RlOgo+PiA+Pj4+Pk9uIDIw LzA1LzIwMjUgMTc6NDksIERlZXBhayBHdXB0YSB3cm90ZToKPj4gPj4+Pj4+SSBkaWQgZ2l2ZSB0 aGlzIHBhdGNoIG15IFJCIGFuZCBoYWQgcGxhbm5lZCB0byBjb21lIGJhY2sgdG8gaXQgdG8gc2Vl Cj4+ID4+Pj4+PmlmIGl0IGltcGFjdHMgY2ZpIHJlbGF0ZWQgcGF0Y2hlcy4gVGhhbmtzIHRvIGFs ZXggZm9yIGJyaW5pZ25nIHRvIG15Cj4+ID4+Pj4+PmF0dGVudGlvbiBhZ2Fpbi4gQXMgaXQgc3Rh bmRzIHRvZGF5LCBpdCBkb2Vzbid0IGltcGFjdCBjZmkgcmVsYXRlZAo+PiA+Pj4+Pj5jaGFuZ2Vz IGJ1dCBJJ3ZlIHNvbWUgY29uY2VybnMuCj4+ID4+Pj4+Pgo+PiA+Pj4+Pj5PdmVyYWxsIEkgZG8g YWdyZWUgd2Ugc2hvdWxkIHJlZHVjZSBudW1iZXIgb2YgU1NUQVRVUyBhY2Nlc3Nlcy4KPj4gPj4+ Pj4+Cj4+ID4+Pj4+PkNvdXBsZSBvZiBxdWVzdGlvbnMgb24gaW50cm9kdWNpbmcgbmV3IGBzc3Rh dHVzYCBmaWVsZCAoaW5saW5lKQo+PiA+Pj4+Pj4KPj4gPj4+Pj4+T24gVHVlLCBBcHIgMjIsIDIw MjUgYXQgMDQ6MDE6MzVQTSAtMDcwMCwgRGVlcGFrIEd1cHRhIHdyb3RlOgo+PiA+Pj4+Pj4+T24g VGh1LCBBcHIgMTAsIDIwMjUgYXQgMDc6MDU6MjJBTSArMDAwMCwgQ3lyaWwgQnVyIHdyb3RlOgo+ PiA+Pj4+Pj4+PkZyb206IEJlbiBEb29rcyA8YmVuLmRvb2tzQGNvZGV0aGluay5jby51az4KPj4g Pj4+Pj4+Pj4KPj4gPj4+Pj4+Pj5XaGVuIHRocmVhZHMvdGFza3MgYXJlIHN3aXRjaGVkIHdlIG5l ZWQgdG8gZW5zdXJlIHRoZSBvbGQKPj4gPj4+PmV4ZWN1dGlvbidzCj4+ID4+Pj4+Pj4+U1JfU1VN IHN0YXRlIGlzIHNhdmVkIGFuZCB0aGUgbmV3IHRocmVhZCBoYXMgdGhlIG9sZCBTUl9TVU0gc3Rh dGUKPj4gPj4+Pj4+Pj5yZXN0b3JlZC4KPj4gPj4+Pj4+Pj4KPj4gPj4+Pj4+Pj5UaGUgaXNzdWUg d2FzIHNlZW4gdW5kZXIgaGVhdnkgbG9hZCBlc3BlY2lhbGx5IHdpdGggdGhlCj4+ID4+Pj5zeXot c3RyZXNzIHRvb2wKPj4gPj4+Pj4+Pj5ydW5uaW5nLCB3aXRoIGNyYXNoZXMgYXMgZm9sbG93cyBp biBzY2hlZHVsZV90YWlsOgo+PiA+Pj4+Pj4+Pgo+PiA+Pj4+Pj4+PlVuYWJsZSB0byBoYW5kbGUg a2VybmVsIGFjY2VzcyB0byB1c2VyIG1lbW9yeSB3aXRob3V0Cj4+ID4+Pj51YWNjZXNzIHJvdXRp bmVzCj4+ID4+Pj4+Pj4+YXQgdmlydHVhbCBhZGRyZXNzIDAwMDAwMDAwMjc0OWYwZDAKPj4gPj4+ Pj4+Pj5Pb3BzIFsjMV0KPj4gPj4+Pj4+Pj5Nb2R1bGVzIGxpbmtlZCBpbjoKPj4gPj4+Pj4+Pj5D UFU6IDEgUElEOiA0ODc1IENvbW06IHN5ei1leGVjdXRvci4wIE5vdCB0YWludGVkCj4+ID4+Pj4+ Pj4+NS4xMi4wLXJjMi1zeXprYWxsZXItMDA0NjctZzBkNzU4OGFiOWVmOSAjMAo+PiA+Pj4+Pj4+ PkhhcmR3YXJlIG5hbWU6IHJpc2N2LXZpcnRpbyxxZW11IChEVCkKPj4gPj4+Pj4+Pj5lcGMgOiBz Y2hlZHVsZV90YWlsKzB4NzIvMHhiMiBrZXJuZWwvc2NoZWQvY29yZS5jOjQyNjQKPj4gPj4+Pj4+ Pj5yYSA6IHRhc2tfcGlkX3ZuciBpbmNsdWRlL2xpbnV4L3NjaGVkLmg6MTQyMSBbaW5saW5lXQo+ PiA+Pj4+Pj4+PnJhIDogc2NoZWR1bGVfdGFpbCsweDcwLzB4YjIga2VybmVsL3NjaGVkL2NvcmUu Yzo0MjY0Cj4+ID4+Pj4+Pj4+ZXBjIDogZmZmZmZmZTAwMDA4YzhiMCByYSA6IGZmZmZmZmUwMDAw OGM4YWUgc3AgOiBmZmZmZmZlMDI1ZDE3ZWMwCj4+ID4+Pj4+Pj4+Z3AgOiBmZmZmZmZlMDA1ZDI1 Mzc4IHRwIDogZmZmZmZmZTAwZjBkMDAwMCB0MCA6IDAwMDAwMDAwMDAwMDAwMDAKPj4gPj4+Pj4+ Pj50MSA6IDAwMDAwMDAwMDAwMDAwMDEgdDIgOiAwMDAwMDAwMDAwMGY0MjQwIHMwIDogZmZmZmZm ZTAyNWQxN2VlMAo+PiA+Pj4+Pj4+PnMxIDogMDAwMDAwMDAyNzQ5ZjBkMCBhMCA6IDAwMDAwMDAw MDAwMDAwMmEgYTEgOiAwMDAwMDAwMDAwMDAwMDAzCj4+ID4+Pj4+Pj4+YTIgOiAxZmZmZmZmYzBj ZmFjNTAwIGEzIDogZmZmZmZmZTAwMDBjODBjYyBhNCA6IDVhZTlkYjkxYzE5YmJlMDAKPj4gPj4+ Pj4+Pj5hNSA6IDAwMDAwMDAwMDAwMDAwMDAgYTYgOiAwMDAwMDAwMDAwZjAwMDAwIGE3IDogZmZm ZmZmZTAwMDA4MmViYQo+PiA+Pj4+Pj4+PnMyIDogMDAwMDAwMDAwMDA0MDAwMCBzMyA6IGZmZmZm ZmUwMGVlZjk2YzAgczQgOiBmZmZmZmZlMDIyYzc3ZmUwCj4+ID4+Pj4+Pj4+czUgOiAwMDAwMDAw MDAwMDA0MDAwIHM2IDogZmZmZmZmZTA2N2Q3NGUwMCBzNyA6IGZmZmZmZmUwNjdkNzQ4NTAKPj4g Pj4+Pj4+Pj5zOCA6IGZmZmZmZmUwNjdkNzNlMTggczkgOiBmZmZmZmZlMDY3ZDc0ZTAwIHMxMDog ZmZmZmZmZTAwZWVmOTZlOAo+PiA+Pj4+Pj4+PnMxMTogMDAwMDAwYWU2Y2RmODM2OCB0MyA6IDVh ZTlkYjkxYzE5YmJlMDAgdDQgOiBmZmZmZmZjNDA0M2NhZmIyCj4+ID4+Pj4+Pj4+dDUgOiBmZmZm ZmZjNDA0M2NhZmJhIHQ2IDogMDAwMDAwMDAwMDA0MDAwMAo+PiA+Pj4+Pj4+PnN0YXR1czogMDAw MDAwMDAwMDAwMDEyMCBiYWRhZGRyOiAwMDAwMDAwMDI3NDlmMGQwIGNhdXNlOgo+PiA+Pj4+Pj4+ PjAwMDAwMDAwMDAwMDAwMGYKPj4gPj4+Pj4+Pj5DYWxsIFRyYWNlOgo+PiA+Pj4+Pj4+Pls8ZmZm ZmZmZTAwMDA4YzhiMD5dIHNjaGVkdWxlX3RhaWwrMHg3Mi8weGIyCj4+ID4+Pj5rZXJuZWwvc2No ZWQvY29yZS5jOjQyNjQKPj4gPj4+Pj4+Pj5bPGZmZmZmZmUwMDAwMDU1NzA+XSByZXRfZnJvbV9l eGNlcHRpb24rMHgwLzB4MTQKPj4gPj4+Pj4+Pj5EdW1waW5nIGZ0cmFjZSBidWZmZXI6Cj4+ID4+ Pj4+Pj4+IChmdHJhY2UgYnVmZmVyIGVtcHR5KQo+PiA+Pj4+Pj4+Pi0tLVsgZW5kIHRyYWNlIGI1 ZjhmOTIzMWRjODdkZGEgXS0tLQo+PiA+Pj4+Pj4+Pgo+PiA+Pj4+Pj4+PlRoZSBpc3N1ZSBjb21l cyBmcm9tIHRoZSBwdXRfdXNlcigpIGluIHNjaGVkdWxlX3RhaWwKPj4gPj4+Pj4+Pj4oa2VybmVs L3NjaGVkL2NvcmUuYykgZG9pbmcgdGhlIGZvbGxvd2luZzoKPj4gPj4+Pj4+Pj4KPj4gPj4+Pj4+ Pj5hc21saW5rYWdlIF9fdmlzaWJsZSB2b2lkIHNjaGVkdWxlX3RhaWwoc3RydWN0IHRhc2tfc3Ry dWN0ICpwcmV2KQo+PiA+Pj4+Pj4+PnsKPj4gPj4+Pj4+Pj4uLi4KPj4gPj4+Pj4+Pj4gICAgICBp ZiAoY3VycmVudC0+c2V0X2NoaWxkX3RpZCkKPj4gPj4+Pj4+Pj4gICAgICAgICAgICAgIHB1dF91 c2VyKHRhc2tfcGlkX3ZucihjdXJyZW50KSwKPj4gPj4+PmN1cnJlbnQtPnNldF9jaGlsZF90aWQp Owo+PiA+Pj4+Pj4+Pi4uLgo+PiA+Pj4+Pj4+Pn0KPj4gPj4+Pj4+Pj4KPj4gPj4+Pj4+Pj50aGUg cHV0X3VzZXIoKSBtYWNybyBjYXVzZXMgdGhlIGNvZGUgc2VxdWVuY2UgdG8gY29tZSBvdXQgYXMK Pj4gPj4+PmZvbGxvd3M6Cj4+ID4+Pj4+Pj4+Cj4+ID4+Pj4+Pj4+MTogICAgX19lbmFibGVfdXNl cl9hY2Nlc3MoKQo+PiA+Pj4+Pj4+PjI6ICAgIHJlZyA9IHRhc2tfcGlkX3ZucihjdXJyZW50KTsK Pj4gPj4+Pj4+Pj4zOiAgICAqY3VycmVudC0+c2V0X2NoaWxkX3RpZCA9IHJlZzsKPj4gPj4+Pj4+ Pj40OiAgICBfX2Rpc2FibGVfdXNlcl9hY2Nlc3MoKQo+PiA+Pj4+Pj4+Pgo+PiA+Pj4+Pj4+PlRo ZSBwcm9ibGVtIGlzIHRoYXQgd2UgbWF5IGhhdmUgYSBzbGVlcGluZyBmdW5jdGlvbiBhcwo+PiA+ Pj4+YXJndW1lbnQgd2hpY2gKPj4gPj4+Pj4+Pj5jb3VsZCBjbGVhciBTUl9TVU0gY2F1c2luZyB0 aGUgcGFuaWMgYWJvdmUuIFRoaXMgd2FzIGZpeGVkIGJ5Cj4+ID4+Pj4+Pj4+ZXZhbHVhdGluZyB0 aGUgYXJndW1lbnQgb2YgdGhlIHB1dF91c2VyKCkgbWFjcm8gb3V0c2lkZSB0aGUKPj4gPj4+PnVz ZXItZW5hYmxlZAo+PiA+Pj4+Pj4+PnNlY3Rpb24gaW4gY29tbWl0IDI4NWE3NmJiMmNmNSAoInJp c2N2OiBldmFsdWF0ZSBwdXRfdXNlcigpCj4+ID4+Pj5hcmcgYmVmb3JlCj4+ID4+Pj4+Pj4+ZW5h YmxpbmcgdXNlciBhY2Nlc3MiKSIKPj4gPj4+Pj4+Pj4KPj4gPj4+Pj4+Pj5JbiBvcmRlciBmb3Ig cmlzY3YgdG8gdGFrZSBhZHZhbnRhZ2Ugb2YgdW5zYWZlX2dldC9wdXRfWFhYKCkKPj4gPj4+Pm1h Y3JvcyBhbmQKPj4gPj4+Pj4+Pj50byBhdm9pZCB0aGUgc2FtZSBpc3N1ZSB3ZSBoYWQgd2l0aCBw dXRfdXNlcigpIGFuZCBzbGVlcGluZwo+PiA+Pj4+ZnVuY3Rpb25zIHdlCj4+ID4+Pj4+Pj4+bXVz dCBlbnN1cmUgY29kZSBmbG93IGNhbiBnbyB0aHJvdWdoIHN3aXRjaF90bygpIGZyb20gd2l0aGlu Cj4+ID4+Pj5hIHJlZ2lvbiBvZgo+PiA+Pj4+Pj4+PmNvZGUgd2l0aCBTUl9TVU0gZW5hYmxlZCBh bmQgY29tZSBiYWNrIHdpdGggU1JfU1VNIHN0aWxsCj4+ID4+Pj5lbmFibGVkLiBUaGlzCj4+ID4+ Pj4+Pj4+cGF0Y2ggYWRkcmVzc2VzIHRoZSBwcm9ibGVtIGFsbG93aW5nIGZ1dHVyZSB3b3JrIHRv IGVuYWJsZQo+PiA+Pj4+ZnVsbCB1c2Ugb2YKPj4gPj4+Pj4+Pj51bnNhZmVfZ2V0L3B1dF9YWFgo KSBtYWNyb3Mgd2l0aG91dCBuZWVkaW5nIHRvIHRha2UgYSBDU1IKPj4gPj4+PmJpdCBmbGlwIGNv c3QKPj4gPj4+Pj4+Pj5vbiBldmVyeSBhY2Nlc3MuIE1ha2Ugc3dpdGNoX3RvKCkgc2F2ZSBhbmQg cmVzdG9yZSBTUl9TVU0uCj4+ID4+Pj4+Pj4+Cj4+ID4+Pj4+Pj4+UmVwb3J0ZWQtYnk6IHN5emJv dCtlNzRiOTRmZTYwMWFiOTU1MmQ2OUBzeXprYWxsZXIuYXBwc3BvdG1haWwuY29tCj4+ID4+Pj4+ Pj4+U2lnbmVkLW9mZi1ieTogQmVuIERvb2tzIDxiZW4uZG9va3NAY29kZXRoaW5rLmNvLnVrPgo+ PiA+Pj4+Pj4+PlNpZ25lZC1vZmYtYnk6IEN5cmlsIEJ1ciA8Y3lyaWxidXJAdGVuc3RvcnJlbnQu Y29tPgo+PiA+Pj4+Pj4+Pi0tLQo+PiA+Pj4+Pj4+PmFyY2gvcmlzY3YvaW5jbHVkZS9hc20vcHJv Y2Vzc29yLmggfCAxICsKPj4gPj4+Pj4+Pj5hcmNoL3Jpc2N2L2tlcm5lbC9hc20tb2Zmc2V0cy5j ICAgIHwgNSArKysrKwo+PiA+Pj4+Pj4+PmFyY2gvcmlzY3Yva2VybmVsL2VudHJ5LlMgICAgICAg ICAgfCA4ICsrKysrKysrCj4+ID4+Pj4+Pj4+MyBmaWxlcyBjaGFuZ2VkLCAxNCBpbnNlcnRpb25z KCspCj4+ID4+Pj4+Pj4+Cj4+ID4+Pj4+Pj4+ZGlmZiAtLWdpdCBhL2FyY2gvcmlzY3YvaW5jbHVk ZS9hc20vcHJvY2Vzc29yLmgKPj4gPj4+Pj4+Pj5iL2FyY2gvcmlzY3YvaW5jbHVkZS8gYXNtL3By b2Nlc3Nvci5oCj4+ID4+Pj4+Pj4+aW5kZXggNWY1NmViOWQxMTRhLi41OGZkMTFjODlmZTkgMTAw NjQ0Cj4+ID4+Pj4+Pj4+LS0tIGEvYXJjaC9yaXNjdi9pbmNsdWRlL2FzbS9wcm9jZXNzb3IuaAo+ PiA+Pj4+Pj4+PisrKyBiL2FyY2gvcmlzY3YvaW5jbHVkZS9hc20vcHJvY2Vzc29yLmgKPj4gPj4+ Pj4+Pj5AQCAtMTAzLDYgKzEwMyw3IEBAIHN0cnVjdCB0aHJlYWRfc3RydWN0IHsKPj4gPj4+Pj4+ Pj4gICAgc3RydWN0IF9fcmlzY3ZfZF9leHRfc3RhdGUgZnN0YXRlOwo+PiA+Pj4+Pj4+PiAgICB1 bnNpZ25lZCBsb25nIGJhZF9jYXVzZTsKPj4gPj4+Pj4+Pj4gICAgdW5zaWduZWQgbG9uZyBlbnZj Zmc7Cj4+ID4+Pj4+Pj4+KyAgICB1bnNpZ25lZCBsb25nIHN0YXR1czsKPj4gPj4+Pj4+Cj4+ID4+ Pj4+PkRvIHdlIHJlYWxseSBuZWVkIGEgbmV3IG1lbWJlciBmaWVsZCBpbiBgdGhyZWFkX3N0cnVj dGAuIFdlCj4+ID4+Pj5hbHJlYWR5IGhhdmUKPj4gPj4+Pj4+YHNzdGF0dXNgIGluIGBwdF9yZWdz YCB3aGljaCByZWZsZWN0cyBvdmVyYWxsIGV4ZWN1dGlvbiBlbnZpcm9ubWVudAo+PiA+Pj4+Pj5z aXR1YXRpb24KPj4gPj4+Pj4+Zm9yIGN1cnJlbnQgdGhyZWFkLiBUaGlzIGdldHMgc2F2ZWQgYW5k IHJlc3RvcmVkIG9uIHRyYXAgZW50cnkKPj4gPj4+PmFuZCBleGl0Lgo+PiA+Pj4+Pj4KPj4gPj4+ Pj4+SWYgd2UgcHV0IGBzdGF0dXNgIGluIGB0aHJlYWRfc3RydWN0YCBpdCBjcmVhdGVzIGFtYmln dWl0eSBpbiB0ZXJtcwo+PiA+Pj4+Pj5vZiB3aGljaAo+PiA+Pj4+Pj5gc3RhdHVzYCB0byBzYXZl IHRvIGFuZCBwaWNrIGZyb20gZnJvbSBmdXR1cmUgbWFpbnRhaW5pYmlsaXR5Cj4+ID4+Pj4+PnB1 cnBvc2VzIGFzIHRoZQo+PiA+Pj4+Pj5maWVsZHMgZ2V0IGludHJvZHVjZWQgdG8gdGhpcyBDU1Iu Cj4+ID4+Pj4+Pgo+PiA+Pj4+Pj5XaHkgY2FuJ3Qgd2UgYWNjZXNzIGN1cnJlbnQgdHJhcCBmcmFt ZSdzIGBzc3RhdHVzYCBpbWFnZSBpbgo+PiA+Pj4+Pj5gX19zd2l0Y2hfdG9gIHRvCj4+ID4+Pj4+ PnNhdmUgYW5kIHJlc3RvcmU/Cj4+ID4+Pj4+Pgo+PiA+Pj4+Pj5MZXQgbWUga25vdyBpZiBJIGFt IG1pc3Npbmcgc29tZXRoaW5nIG9idmlvdXMgaGVyZS4gSWYgdGhlcmUgaXMgYQo+PiA+Pj4+Pj5j b21wbGljYXRpb24sCj4+ID4+Pj4+PkkgYW0gbWlzc2luZyBoZXJlIGFuZCB3ZSBkbyBlbmQgdXAg dXNpbmcgdGhpcyBtZW1iZXIgZmllbGQsIEkgd291bGQKPj4gPj4+Pj4+cmVuYW1lIGl0Cj4+ID4+ Pj4+PnRvIHNvbWV0aGluZyBsaWtlIGBzdGF0dXNfa2VybmVsYCB0byByZWZsZWN0IHRoYXQuIFNv IHRoYXQgZnV0dXJlCj4+ID4+Pj4+PmNoYW5nZXMgYXJlCj4+ID4+Pj4+PmNvZ25pemFudCBvZiB0 aGUgZmFjdCB0aGF0IHdlIGhhdmUgc3BsaXQgYHN0YXR1c2AuIE9uZSBmb3Iga2VybmVsCj4+ID4+ Pj4+PmV4ZWN1dGlvbiBlbnYKPj4gPj4+Pj4+cGVyIHRocmVhZCBhbmQgb25lIGZvciBjb250cm9s bGluZyB1c2VyIGV4ZWN1dGlvbiBlbnYgcGVyIHRocmVhZC4KPj4gPj4+Pj4KPj4gPj4+Pj5UaGlz IGlzIHNvIGxvbmcgYWdvIG5vdyBJIGNhbm5vdCByZW1lbWJlciBpZiB0aGVyZSB3YXMgYW55IHNz dGF0dXMgaW4KPj4gPj4+Pj50aGUgcHRfcmVncyBmaWVsZCwKPj4gPj4+Pgo+PiA+Pj4+RlMvVlMg Yml0cyBlbmNvZGUgc3RhdHVzIG9mIGZsb2F0aW5nIHBvaW50IGFuZCB2ZWN0b3Igb24KPj4gPj4+ PnBlci10aHJlYWQgYmFzaXMuCj4+ID4+Pj5TbyBgc3RhdHVzYCBoYXMgYmVlbiBwYXJ0IG9mIGBw dF9yZWdzYCBmb3IgcXVpdGUgYSB3aGlsZS4KPj4gPj4+Pgo+PiA+Pj4+PiBhbmQgaWYga2VybmVs IHRocmVhZHMgaGF2ZSB0aGUgc2FtZSBjb250ZXh0IGFzIHRoZWlyCj4+ID4+Pj4+dXNlcmxhbmQg cGFydHMuCj4+ID4+Pj4KPj4gPj4+PkkgZGlkbid0IG1lYW4ga2VybmVsIHRocmVhZC4gV2hhdCBJ IG1lYW50IHdhcyBrZXJuZWwgZXhlY3V0aW9uCj4+ID4+Pj5lbnZpcm9ubWVudAo+PiA+Pj4+cGVy LXRocmVhZC4gQSB1c2VybGFuZCB0aHJlYWQgZG9lcyBzcGVuZCBzb21ldGltZSBpbiBrZXJuZWwg YW5kCj4+ID4+Pj5rZXJuZWwgZG9lcwo+PiA+Pj4+dGhpbmdzIG9uIGl0cyBiZWhhbGYuIE9uZSBv ZiB0aG9zZSB0aGluZyBpcyB0b3VjaGluZyB1c2VyIG1lbW9yeQo+PiA+Pj4+YW5kIHRoYXQKPj4g Pj4+PnJlcXVpcmVzIG11Y2tpbmcgd2l0aCB0aGlzIENTUi4gU28gd2hhdCBJIG1lYW50IHdhcyBh cmUgd2UKPj4gPj4+PnNwbGl0dGluZyBgc3RhdHVzYAo+PiA+Pj4+b24gcGVyLXRocmVhZCBiYXNp cyBmb3IgdGhlaXIgdGltZSBzcGVudCBpbiB1c2VyIGFuZCBrZXJuZWwuCj4+ID4+Pj4KPj4gPj4+ PkdldHRpbmcgYmFjayB0byBvcmlnaW5hbCBxdWVzdGlvbi0tCj4+ID4+Pj5BcyBJIHNhaWQsIGVh Y2ggdGhyZWFkIHNwZW5kcyBzb21ldGltZSBpbiB1c2VyIG9yIGluIGtlcm5lbC4KPj4gPj4+PmBz dGF0dXNgIGluCj4+ID4+Pj5gcHRfcmVnc2AgaXMgc2F2ZWQgb24gdHJhcCBlbnRyeSBhbmQgcmVz dG9yZWQgb24gdHJhcCBleGl0LiBJbiBhIHNlbnNlLAo+PiA+Pj4+YHN0YXR1c2AgZmllbGQgaW4g YHB0X3JlZ3NgIGlzIHJlZmxlY3RpbmcgZXhlY3V0aW9uIHN0YXR1cyBvZgo+PiA+Pj4+dGhlIHRo cmVhZCBvbiBwZXIKPj4gPj4+PnRyYXAgYmFzaXMuIEludHJvZHVjaW5nIGBzdGF0dXNgIGluIGB0 aHJlYWRfc3RydWN0YCBjcmVhdGVzIGEKPj4gPj4+PmNvbmZ1c2lvbiAoaWYgbm90Cj4+ID4+Pj5m b3IgdG9kYXksIGNlcnRhaW5seSBmb3IgZnV0dXJlKSBvZiB3aGljaCBgc3RhdHVzYCB0byBwaWNr IGZyb20KPj4gPj4+PndoZW4gd2UgYXJlCj4+ID4+Pj5kb2luZyBzYXZlL3Jlc3RvcmUuCj4+ID4+ Pgo+PiA+Pj5JIGFncmVlIHRoYXQgaXQncyBhIGNvbmZ1c2lvbi4gc3N0YXR1cyBpcyBhbHJlYWR5 IHNhdmVkIG9uIHB0X3JlZ3Mgb24KPj4gPj4+dHJhcCBlbnRyaWVzL3JldHVybiwgYWRkaW5nIGFu b3RoZXIgZW50cnkgYWRkcyBjb2RlIGNvbXBsZXhpdHkgYW5kCj4+ID4+Pm1ha2VzIGRhdGEgaW5j b25zaXN0ZW50LiBCdXQsIHBlcmhhcHMgd2UnZCBldmVudHVhbGx5IG5lZWQgc29tZXRoaW5nCj4+ ID4+Pmxpa2UgdGhpcyAoSSB3aWxsIGV4cGxhaW4gd2h5KS4gU3RpbGwsIHRoZXJlIG1pZ2h0IGJl IGEgYmV0dGVyCj4+ID4+PmFwcHJvYWNoLgo+PiA+Pj4KPj4gPj4+WWVzLCB3ZSBjYW4gYWx3YXlz IHJlZmxlY3QgcHRfcmVncyBmb3Igc3N0YXR1cy4gV2UgYWxsIGtub3cgdGhhdAo+PiA+Pj5wdF9y ZWdzIHJlZmxlY3RzIHNzdGF0dXMgYXQgdHJhcCBlbnRyeSwgYW5kIHRoZSBwdF9yZWdzIGF0IHNj aGVkdWxlcgo+PiA+Pj5wb2ludCByZWZlcnMgdG8gInVzZXIncyIgcHRfcmVncyB3aGVuZXZlciBp dCBmaXJzdCBlbnRlcnMga2VybmVsCj4+ID4+Pm1vZGUuIEhlcmUKPj4gPj4+YXJlIHJlYXNvbnMg d2h5IFNSX1NVTSBoZXJlIG1heSBvciBtYXkgbm90IGJlIHByb3Blcmx5IHRyYWNrZWQuIEZpcnN0 LAo+PiA+Pj5pZiB0aGlzIGlzIGEgdHJhcCBpbnRyb2R1Y2VkIGNvbnRleHQgc3dpdGNoIChzdWNo IGFzIGludGVycnVwdGluZyBpbiBhCj4+ID4+PnByZWVtcHRpYmxlIGNvbnRleHQgYWZ0ZXIgd2Ug bWFudWFsbHkgZW5hYmxlIHVzZXIgYWNjZXNzIGluIHB1dF91c2VyKSwKPj4gPj4+dGhlbiBTUl9T VU0gaXMgc2F2ZWQgc29tZXdoZXJlIGluIHRoZSBrZXJuZWwgc3RhY2ssIGFuZCBpcyBub3QKPj4g Pj4+cmVmZXJlbmNlLWFibGUgd2l0aCB0YXNrX3B0X3JlZyBkdXJpbmcgY29udGV4dCBzd2l0Y2gu IEJ1dCB3ZSBhcmUgc2FmZQo+PiA+Pj5iZWNhdXNlIHRoZSB0cmFwIGV4aXQgYXNtIHdvdWxkIGhl bHAgdXMgcmVzdG9yZSB0aGUgY29ycmVjdCBTUl9TVU0KPj4gPj4+YmFjay4gSG93ZXZlciwgaWYg dGhpcyBpcyBhIHNlbGYtaW5pdGlhdGluZyBjb250ZXh0IHN3aXRjaCAoY2FsbGluZwo+PiA+Pj5p bnRvIHNjaGVkdWxlKCkpLCB0aGVuIFNSX1NVTSBpcyBub3Qgc2F2ZWQgYW55d2hlcmUsIGFuZCBw b3NzaWJseQo+PiA+Pj5jYXVzaW5nIHRoaXMgZXJyb3IuCj4+ID4+Pgo+PiA+Pj5QcmVlbXB0aWJs ZSBWZWN0b3IgaW4gdGhlIGtlcm5lbCBtb2RlIGFsc28gaGFkIHRoaXMgcHJvYmxlbSB3aGVyZSBh Cj4+ID4+PnNlbGYtaW5pdGlhdGluZyBjb250ZXh0IHN3aXRjaCBsb3NlcyB0aGUgdHJhY2sgb2Yg c3N0YXR1cy52cy4gVGhlIHdheQo+PiA+Pj5JIG1hbmFnZWQgaXQgaXMgdG8gdHJhY2sgdGhlIFZT IGJpdCBhdCBjb250ZXh0IHN3aXRjaCB0aW1lLiBIb3dldmVyLAo+PiA+Pj50aGlzIGJ1ZyBzaG93 cyB0aGF0IHBlb3BsZSBhcmUgcmVwZWF0ZWRseSBmYWNpbmcgdGhlIHByb2JsZW0sIGFuZAo+PiA+ Pj5tYXliZSBpdCBzdWdnZXN0cyB0aGF0IHdlJ2QgbmVlZCBhIGJldHRlciB3YXkgb2YgbWFuYWdp bmcgc3N0YXR1cwo+PiA+Pj5hY3Jvc3MgY29udGV4dCBzd2l0Y2hlcy4gR2l2ZW4gdGhlIGNvbXBs ZXggbmF0dXJlIG9mIHRoaXMgcmVnaXN0ZXIsCj4+ID4+PndoaWNoIGFsc28gdG91Y2hlcyB0aGUg aW50ZXJydXB0IGVuYWJsZSBzdGF0dXMsIEkgZG9uJ3QgdGhpbmsgbmFpdmVseQo+PiA+Pj5zYXZp bmcvcmVzdG9yaW5nIHRoZSBlbnRpcmUgcmVnaXN0ZXIgaXMgdGhlIHdheSB0byBnby4gTWF5YmUg dGhlCj4+ID4+PnZhcmlhYmxlIGRlc2VydmVzIGEgbW9yZSBzcGVjaWZpYyBuYW1pbmcgYW5kIGRv Y3VtZW50YXRpb24uIEFuZCBpZgo+PiA+Pj53ZSdkIG5lZWQgYSBjZW50cmFsaXplZCBwbGFjZSBm b3IgbWFuYWdpbmcgdGhlc2Ugc3RhdHVzZXMsIHRoZW4gaXQKPj4gPj4+YWxzbyBoYXMgdG8gdGFr ZSBjYXJlIG9mIHNzdGF0dXMuVlMuCj4+ID4KPj4gPgo+PiA+QW5keSwgdGhhbmtzIGZvciB0aGUg cHJlY2lzZSBleHBsYW5hdGlvbiBvZiB0aGUgcHJvYmxlbSA6KQo+Cj5UaGFua3MgZm9yIHJlYWRp bmcgaXQgQWxleCEgSXQncyBteSBiYWQgbWFraW5nIGl0IHdvcmR5Cj4KPj4gPgo+PiA+U28gaXQg dG9vayBtZSBzb21lIHRpbWUgYnV0IGhlcmUgYXJlIG15IHRob3VnaHRzIG9uIHRoaXMuIFdlIHNo b3VsZAo+PiA+dHJlYXQgcHRfcmVncyBhbmQgdGhyZWFkX3N0cnVjdCBkaWZmZXJlbnRseSBhcyB0 aGV5IGRvIG5vdCByZXByZXNlbnQKPj4gPnRoZSBzYW1lIHRoaW5nOgo+PiA+LSBwdF9yZWdzIHJl cHJlc2VudHMgdGhlIGNvbnRleHQgb2YgYSB0aHJlYWQgd2hlbiBpdCB0YWtlcyBhIHRyYXAKPj4g Pi0gdGhyZWFkX3N0cnVjdCByZXByZXNlbnRzIGEgImtlcm5lbC1pbmR1Y2VkIiAob3IgYSAiaW4t a2VybmVsIikKPj4gPmNvbnRleHQgbm90IGNhdXNlZCBieSB0cmFwcwo+Pgo+PiBFeGFjdGx5IHRo ZXkgcmVwcmVzZW50IGRpZmZlcmVudCBjb250ZXh0IG9mIGV4ZWN1dGlvbi4gVHJhcCByZXByZXNl bnRzIGEKPj4gbm9uLWxpbmVhciBjb250cm9sIGZsb3cgY2hhbmdlIGFuZCB0aHVzIGEgZnJlc2gg c3RhcnQgb2YgZXhlY3V0aW9uIGNvbnRyb2wKPj4gZmxvdyBpbnRvIGtlcm5lbCB3aGlsZSBga2Vy bmVsLWluZHVjZWRgIG9uZSdzIGFyZSBhZ2FpbiBub24tbGluZWFyIGJ1dAo+PiBmdWxseSBhIGtl cm5lbC9zb2Z0d2FyZSBjb25zdHJ1Y3QuCj4+Cj4+IEEgZnJlc2ggdHJhcHBlZCBleGVjdXRpb24g Y29udGV4dCBzaG91bGRuJ3QgaGF2ZSBTVU0gc2V0IHdoaWNoIGlzIGhvdyBpdCBpcwo+PiBjdXJy ZW50bHkgaW4ga2VybmVsLiBUaGlzIGJpdCBnZXRzIGNsZWFyZWQgaW4gdHJhcCBlbnRyeSBhbmQg YHNzdGF0dXNgIGdldHMKPj4gc2F2ZWQgaW4gYHB0X3JlZ3NgIChpbmNsdWRpbmcgU1JfSUUpIHNv IHRoYXQgaXQgY291bGQgYmUgcmVzdG9yZWQgd2hlbmV2ZXIKPj4gYHNyZXRgIGhhcHBlbnMuCj4+ Cj4+IFRoZSBwcm9ibGVtIHdlJ2FyZSBzZWVpbmcgaGVyZSBpcyB0d28gZm9sZC0tCj4+Cj4+IDEp IFdlIGRvbid0IHdhbnQgdG8gc2V0IGFuZCBjbGVhciB3aGVuIHdlIGFyZSBhY2Nlc3NpbmcgYXJy YXkvc3RyaW5nIGZvciBlYWNoCj4+ICAgICB3b3JkLiBUaGlzIGlzIHNvZnR3YXJlIHByb2JsZW0g YW5kIHRoaXMgZW50aXJlIHNlcmllcyBpcyBhZGRyZXNzaW5nIGl0Lgo+Pgo+PiAyKSBUbyBhdm9p ZCBmaXJzdCBwcm9ibGVtIHdlIGFyZSBvcHRpbWl6aW5nIHRoZSBhY2Nlc3MgdG8gQ1NSIGJ5IHNl dHRpbmcgaXQKPj4gICAgIG9uY2UgYW5kIGNsZWFyaW5nIGl0IG9uY2UuIEJ1dCBub3cgd2UgZG9u J3Qgd2FudCB0byBsb29zZSB0aGlzIGJpdCBpZiB0aGVyZQo+PiAgICAgd2VyZToKPj4KPj4gICAg ICAgICBhKSB0cmFwIGluIGJldHdlZW4KPj4gICAgICAgICAgYikga2VybmVsIGluZHVjZWQgc2No ZWR1bGUgb3V0Cj4+ICAgICAgICAgIGMpIGEpIGZvbGxvd2VkIGJ5IGIpCj4+ICAgICAgICAgIGQp IGEpIGZvbGxvd2VkIGJ5IGFub3RoZXIgYSkKPj4gICAgICAgICAgZSkgbmVzdGVkIHRyYXBzCj4+ Cj4+IElmIGEpIG9jY3Vycywgd2UgYXJlIGRlZmluaXRsZXkgbG9vc2luZyB0aGUgYml0IGFzIHBl ciBjdXJyZW50IGNvZGUuIElmIGIpCj4+IGhhcHBlbnMgdGhlbiBhbHNvIHRoZSBzYW1lIHNpdHVh dGlvbi4KPj4KPj4gU2F2aW5nIGl0IGluIGB0aHJlYWRfc3RydWN0YCBvbmx5IGFkZHJlc3NlcyBg YmAuIEFuZCBub3QgYGFgLCBgY2AsIGBkYCBhbmQKPj4gYGVgLiBJTUhPIGBlYCBpcyBmYXItZmV0 Y2hlZCBzaXR1YXRpb24gYnV0IEkgYmVsaWV2ZSBgYWAsIGBiYCwgYGNgIGFuZCBgZGAgaGFwcGVu Cj4+IGR1cmluZyBub3JtYWwgcnVudGltZSBvZiBrZXJuZWwuCj4KPlRoZSB0cmFwIGVudHJ5L2V4 aXQgcm91dGluZSBzaG91bGQgYWx3YXlzIHRha2UgY2FyZSBvZiB0cmFwIGNhc2VzLAo+d2hlbmV2 ZXIgdGhlIGtlcm5lbCB0cmFwcywgU1VNIGlzIHNhdmVkIHRvIHB0X3JlZ3Mgc29tZXdoZXJlIGlu IHRoZQo+a2VybmVsIHN0YWNrLiBZZXMsIGEgdGFzayBtYXkgYmUgc2NoZWR1bGVkIG91dCBhZnRl ciBhIHRyYXAsIHdoaWNoIGlzCj5jb21tb24sIGJ1dCBwbGVhc2UgYmUgYXdhcmUgb2YgdGhhdCBh ZnRlciBzY2hlZHVsaW5nIGJhY2sgdG8gdGhlCj5vcmlnaW5hbCB0YXNrLCBpdCB0aGVuIGhhcyB0 byBleGVjdXRlIHRoZSB0cmFwIGV4aXQgYW5kIHRodXMgcmVzdG9yZQo+dGhlIFNVTSBiZWZvcmUg Z29pbmcgYmFjayB0byB0aGUgb3JpZ2luYWwgY29kZSAod2hlcmUgaXQgcmVjZWl2ZXMgYW4KPmV4 Y2VwdGlvbikuCgpZZXMgeW91IGFyZSByaWdodC4gVGhhbmtzIGZvciBjb3JyZWN0aW5nIG1lLgoK QXMgSSBtZW50aW9uZWQgaW4gYW5vdGhlciBmb3JrIG9mIHRoZSB0aHJlYWQuIFRoZSBuZXN0aW5n IG9mIHRyYXBzIGlzIHRha2VuCmNhcmUgb2YgYnkgdHJhcCBlbnRyeS9leGl0LiAKSXQncyBhbGwg YWJvdXQga2VybmVsIGluZHVjZWQgZXZlbnQgdGhlbi4KCklzIHRoZXJlIG5lc3Rpbmcgb2Yga2Vy bmVsIGluZHVjZWQgZXZlbnQ/CklmIHRoZXJlIGlzIG5vIG5lc3RpbmcgdGhlbiBzdXJlIGEgZmll bGQgaW4gYHRocmVhZF9zdHJ1Y3RgIGlzIGZpbmUuCkJ1dCB0aGVuIGluIHRoYXQgY2FzZSBzYXZl L3Jlc3RvcmUgaXMgaW4gYHB0X3JlZ3NgIGlzIGFsc28gZmluZSBhbmQga2VlcAphIHNpbmdsZSBp bWFnZSB3aGljaCB0cnVseSByZXByZXNlbnRzIGN1cnJlbnQgY29udGV4dCBhbmQgdHJhcCB0b2dl dGhlci4KCj4KPj4KPj4gU28gaXQgYWxsIGRlcGVuZHMgb24gbmVzdGluZyBsZXZlbCBvZiB0cmFw cyBzdXBwb3J0ZWQgYnkgcmlzY3Yga2VybmVsLgo+Pgo+PiBJbGx1c3RyYWluZyBgYyArIGRgIGV4 YW1wbGUsIGlmIGtlcm5lbCBjYW4gdGFrZSAyIG5lc3RlZCBsZXZlbCBvZiB0cmFwcyB3aXRoCj4+ IGZpcnN0IHRyYXAgY29udGV4dCBoYXZpbmcgaGFkIHRoZSBTVU0gYml0IHNldCwgYnV0IHRoZSBz ZWNvbmQgdHJhcCBoYWQgaXQgY2xlYXIKPj4gYW5kIG5vdyBjb21lcyB0aGUgc3dpdGNoIG91dCBv ZiB0aGlzIHRocmVhZCwgYXQgdGhpcyBwb2ludCBpZiBpdCB3ZXJlIHNhdmVkIGluCj4+IGB0aHJl YWRfc3RydWN0YCBTVU0gd291bGQgYmUgbG9zdCBmb3IgdGhlIGZpcnN0IHRyYXAuCj4KPk5vLCB0 aGUgdHJhcCBleGl0IGFsd2F5cyByZXN0b3JlcyB0aGUgaW4tY29udGV4dCAoY29ycmVjdCkgc3N0 YXR1cyBiYWNrCj4KPj4KPj4gTGF0ZXIgd2hlbiB0aGUgdGhyZWFkIGdldHMgc3dpdGNoZWQgaW4g YWdhaW4sIHlvdSB3b3VsZCBnbyBpbiAybmQgdHJhcAo+PiBjb250ZXh0IHdpdGhvdXQgU1VNIChi ZWNhdXNlIGB0aHJlYWRfY29udGV4dGAgZGlkbnQgaGFkIGl0IHNhdmVkKSwgd2hpY2ggaXMKPj4g ZmluZS4gQWx0aG91Z2ggd2hlbiAybmQgdHJhcCBjb250ZXh0IGV2ZW50dWFsbHkgcGVyZm9ybXMg YHNyZXRgLCBpdCB3aWxsCj4+IGdvIGJhY2sgdG8gZmlyc3QgdHJhcCBjb250ZXh0IHdoZXJlIFNV TSB3YXMgZXhwZWN0ZWQgdG8gYmUgc2V0IGJlY2F1c2UgaXQKPj4gdG91Y2hpbmcgYSB1c2VyIG1l bW9yeS4KPj4KPj4gQSBnb29kIGV4YW1wbGUgd291bGQgYmUgYSBzeXNjYWxsLCBzbyB0aGF0J3Mg dGhlIGZpcnN0IHRyYXAuIFNVTSBiaXQgaXMgc2V0LAo+PiB0b3VjaGVkIHVzZXIgbWVtb3J5IGFu ZCB0b29rIGEgdHJhcCAocGFnZSBmYXVsdCkuIE5vdyBjb2RlIGlzIGluIHNlY29uZCB0cmFwCj4+ IHdoaWNoIHNob3VsZCBjbGVhciB0aGUgU1VNIGJpdC4gU29tZXdoZXJlIGluIG1lbW9yeSBtYW5h Z2VyIHN0YWNrLCB0aHJlYWQgaXMKPj4gc2NoZWR1bGVkIG91dCBhbmQgbm93IGBzc3RhdHVzYCBp cyBzYXZlZCBpbiBgdGhyZWFkX3N0cnVjdGAuIFRoaXMgaXMgb25seQo+PiBzZXJ2aW5nIGN1cnJl bnQgdHJhcCBjb250ZXh0IG5lZWRzIGFuZCBub3QgdGhlIG9uZSB3aGVyZSBgU1VNYCBuZWVkZWQg dG8gYmUKPj4gc2V0Lgo+Pgo+PiBXZSBjYW4gc3VwcG9ydCBzdWNoIG5lc3Rpbmcgb25seSBieSBl bnN1cmluZyBiZWxvdwo+Pgo+PiBPbiB0cmFwIGVudHJ5IGRvCj4+IC0gc2F2ZSBgc3RhdHVzYCBp biBgcHRfcmVnc2Agb3Igc29tZSBvdGhlciBGSUxPIGRhdGEgc3RydWN0dXJlCj4+IC0gY2xlYXIg U1VNIChhbmQgb3RoZXIgYml0cyBuZWVkZWQgdG8gYmUgY2xlYXJlZCkKPj4KPj4gT24gdHJhcCBy ZXR1cm4gZG8KPj4gLSByZWxvYWQgYHN0YXR1c2AgZnJvbSBgcHRfcmVnc2Agb3Igc29tZSBGSUxP IGRhdGEgc3RydWN0dXJlCj4+Cj4+IFF1aXRlIGFuYWxvZ291cyB0byB3aGF0IHdlIGRvIGZvciBT Ul9JRSBhcyB3ZWxsLgo+Cj5JIGFtIG5vdCBzdXJlIGlmIEkgdW5kZXJzdGFuZCB3aGF0IEZJTE8g aXMsIGJ1dCB0aGUgY3VycmVudCB0cmFwCj5oYW5kbGluZyByb3V0aW5lcyBkbyBzYXZlL3Jlc3Rv cmUgc3N0YXR1cywgd2hpY2ggY2FuIGJlIGZvdW5kIGF0Cj5oYW5kbGVfZXhjZXB0aW9uIGFuZCBy ZXRfZnJvbV9leGNlcHRpb24sIGFzIG9mIHRvZGF5Lgo+Cj4+Cj4+ID4KPj4gPlRoYXQncyB3aHkg SSBkb24ndCByZWFsbHkgbGlrZSBEZWVwYWsncyBwcm9wb3NhbCBiZWxvdyBhcyBpdCBtaXhlcwo+ PiA+Ym90aCBhbmQgSSBmaW5kIGl0IHRyaWNreS4KPj4gPgo+PiA+SSBjYW4ndCBmaW5kIGEgc2l0 dWF0aW9uIHdoZXJlIHNhdmluZy9yZXN0b3JpbmcgdGhlIGVudGlyZSBzc3RhdHVzIGF0Cj4+ID5j b250ZXh0LXN3aXRjaCBpcyBhIHByb2JsZW0gdGhvdWdoLCBkb2VzIGFueW9uZSBoYXZlIHN1Y2gg dGhpbmcgaW4KPj4gPm1pbmQ/Cj4KPkkgYWdyZWUgdGhhdCB3ZSBzaG91bGQga2VlcCB0cmFjayBv ZiBzc3RhdHVzIHNvbWV3aGVyZSBhbmQgYmUgZXhwbGljaXQKPmFib3V0IHdoYXQgY29udGV4dCBp dCB0cmFja3MuCj4KPnNzdGF0dXMgbm90IGp1c3QgdHJhY2tzIHBlci10aHJlYWQgc3RhdHVzLCBz b21lIGFyZSBtYWNoaW5lLXdpZGUuCj5UaG91Z2ggX19zd2l0Y2hfdG8gYXJlIGFsd2F5cyBjYWxs ZWQgd2l0aCBpbnRlcnJ1cHQgZGlzYWJsZWQsIEkgdGhpbmsKPmNvbmNlcHR1YWxseSBpbnRlcnJ1 cHQgZW5hYmxlIHN0YXR1cyBzaG91bGQgbm90IGJlIHNhdmVkL3Jlc3RvcmUgb24gYQo+cGVyLXRo cmVhZCBiYXNpcy4KPgo+SnVzdCBGWUkgdGhhdCBzb21lIHN0YXR1c2VzIGFyZSBjdXJyZW50bHkg bWFuYWdlZCBieSBpbmRpdmlkdWFsCj5tb2R1bGVzIChzdWNoIGFzIHRoZSBsaXZlIHNzdGF0dXMu VlMgYXJlIG1hbmFnZWQgaW4gYXNtL3ZlY3Rvci5oKS4gV2UKPmNhbiBkaXNjdXNzIHdoYXQgaXMg cHJlZmVyZWQuIFRoZSBmaW5hbCBwYXRjaCBzaG91bGQgdGFrZSBjYXJlIG9mCj50aGlzLCBvciBz aG91bGQgZG9jdW1lbnQgdGhhdCBWUyBpcyBtYW5hZ2VkIGVsc2V3aGVyZSwgaWYgd2Ugd291bGQK Pmxpa2UgYSBjZW50cmFsaXplZCBzc3RhdHVzIG1hbmFnZW1lbnQuCj4KPlBlcnNvbmFsbHksIEkg d291bGQgcHJlZmVyIGEgY2VudHJhbGl6ZWQgc3N0YXR1cyBtYW5hZ2VtZW50IHRoYXQgb25seQo+ dG91Y2hlcyBTVU0uIFRoaXMgcHJldmVudHMgZHVwbGljYXRpbmcgY29uZGl0aW9uIG1hdGNoaW5n cyBmb3IgdmVjdG9yCj5vdXQgdG8gb3RoZXIgcGxhY2VzLiBCdXQgbWF5YmUgdGhlcmUgYXJlIGJl dHRlciB3YXlzCj4KPlRoYW5rcywKPkFuZHkKPgo+Cj4KPgo+PiA+Cj4+ID5GaW5hbGx5IEkgdW5k ZXJzdGFuZCB0aGF0IGhhdmluZyBhbm90aGVyIGNvcHkgb2Ygc3N0YXR1cyBpbgo+PiA+dGhyZWFk X3N0cnVjdCBpcyBub3QgaW50dWl0aXZlIGFuZCB3ZSBzaG91bGQsIGVpdGhlciBleHBsYWluIHdo eSBvcgo+PiA+b25seSBzdG9yZSB0aGUgU1VNIGJpdCAobGlrZSBmb3Igc3N0YXR1cy5WUykuCj4+ ID4KPj4gPlBsZWFzZSBjb250aW51ZSB0aGUgZGlzY3Vzc2lvbiBhcyB3ZSBuZWVkIHRvIGZpbmQg YSBzb2x1dGlvbiB0aGF0Cj4+ID5wbGVhc2VzIGV2ZXJ5b25lIHNvb24gOikKPj4gPgo+PiA+VGhh bmtzIGFsbCBmb3IganVtcGluZyBpbiwKPj4gPgo+PiA+QWxleAo+PiA+Cj4+ID4KPj4gPj4KPj4g Pj4KPj4gPj5JTUhPLCB0aGUgcHJvYmxlbSB3ZSBhcmUgdHJ5aW5nIHRvIHNvbHZlIGluIHRoaXMg cGF0Y2ggaXMgZWFzaWx5Cj4+ID4+c29sdmFibGUgaW4KPj4gPj5iZWxvdyBtYW5uZXIuCj4+ID4+ Cj4+ID4+Cj4+ID4+ZGlmZiAtLWdpdCBhL2FyY2gvcmlzY3YvaW5jbHVkZS9hc20vc3dpdGNoX3Rv LmgKPj4gPj5iL2FyY2gvcmlzY3YvaW5jbHVkZS9hc20vc3dpdGNoX3RvLmgKPj4gPj5pbmRleCAw ZTcxZWI4MmY5MjAuLjQ5OWQwMGE2ZmI2NyAxMDA2NDQKPj4gPj4tLS0gYS9hcmNoL3Jpc2N2L2lu Y2x1ZGUvYXNtL3N3aXRjaF90by5oCj4+ID4+KysrIGIvYXJjaC9yaXNjdi9pbmNsdWRlL2FzbS9z d2l0Y2hfdG8uaAo+PiA+PkBAIC01OCw2ICs1OCwyMCBAQCBzdGF0aWMgaW5saW5lIHZvaWQgX19z d2l0Y2hfdG9fZnB1KHN0cnVjdAo+PiA+PnRhc2tfc3RydWN0ICpwcmV2LAo+PiA+PiAgICAgICAg ZnN0YXRlX3Jlc3RvcmUobmV4dCwgdGFza19wdF9yZWdzKG5leHQpKTsKPj4gPj4gfQo+PiA+Pgo+ PiA+PitzdGF0aWMgaW5saW5lIHZvaWQgX19zd2l0Y2hfdG9fc3RhdHVzKHN0cnVjdCB0YXNrX3N0 cnVjdCAqcHJldiwKPj4gPj4rICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHN0cnVj dCB0YXNrX3N0cnVjdCAqbmV4dCkKPj4gPj4rewo+PiA+PisgICAgICAgc3RydWN0IHB0X3JlZ3Mg KnJlZ3M7Cj4+ID4+Kwo+PiA+PisgICAgICAgLyogc2F2ZSBzdGF0dXMgKi8KPj4gPj4rICAgICAg IHJlZ3MgPSB0YXNrX3B0X3JlZ3MocHJldik7Cj4+ID4+KyAgICAgICByZWdzLT5zdGF0dXMgPSBj c3JfcmVhZChDU1JfU1RBVFVTKTsKPj4gPj4rCj4+ID4+KyAgICAgICAvKiByZXN0b3JlIHN0YXR1 cyAqLwo+PiA+PisgICAgICAgcmVncyA9IHRhc2tfcHRfcmVncyhuZXh0KTsKPj4gPj4rICAgICAg IGNzcl93cml0ZShDU1JfU1RBVFVTLCByZWdzLT5zdGF0dXMpOwo+PiA+Pit9Cj4+ID4+Kwo+PiA+ PiBzdGF0aWMgX19hbHdheXNfaW5saW5lIGJvb2wgaGFzX2ZwdSh2b2lkKQo+PiA+PiB7Cj4+ID4+ ICAgICAgICByZXR1cm4gcmlzY3ZfaGFzX2V4dGVuc2lvbl9saWtlbHkoUklTQ1ZfSVNBX0VYVF9m KSB8fAo+PiA+PkBAIC0xMTUsNiArMTI5LDcgQEAgZG8KPj4gPj57ICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBcCj4+ID4+ICAgICAgICBzdHJ1 Y3QgdGFza19zdHJ1Y3QgKl9fcHJldiA9IChwcmV2KTsgICAgICAgICAgICBcCj4+ID4+ICAgICAg ICBzdHJ1Y3QgdGFza19zdHJ1Y3QgKl9fbmV4dCA9IChuZXh0KTsgICAgICAgICAgICBcCj4+ID4+ ICAgICAgICBfX3NldF9wcmV2X2NwdShfX3ByZXYtPnRocmVhZCk7ICAgICAgICAgICAgICAgICBc Cj4+ID4+KyAgICAgICBfX3N3aXRjaF90b19zdGF0dXMoX19wcmV2LCBfX25leHQpICAgICAgICAg ICAgICBcCj4+ID4+ICAgICAgICBpZiAoaGFzX2ZwdSgpKSAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICBcCj4+ID4+ICAgICAgICAgICAgICAgIF9fc3dpdGNoX3RvX2ZwdShfX3ByZXYs IF9fbmV4dCk7ICAgICAgICBcCj4+ID4+ICAgICAgICBpZiAoaGFzX3ZlY3RvcigpIHx8IGhhc194 dGhlYWR2ZWN0b3IoKSkgICAgICAgICBcCj4+ID4+ZGlmZiAtLWdpdCBhL2FyY2gvcmlzY3Yva2Vy bmVsL2VudHJ5LlMgYi9hcmNoL3Jpc2N2L2tlcm5lbC9lbnRyeS5TCj4+ID4+aW5kZXggOGQyNTgz N2E5Mzg0Li5hM2I5OGMxYmUwNTUgMTAwNjQ0Cj4+ID4+LS0tIGEvYXJjaC9yaXNjdi9rZXJuZWwv ZW50cnkuUwo+PiA+PisrKyBiL2FyY2gvcmlzY3Yva2VybmVsL2VudHJ5LlMKPj4gPj5AQCAtMTYy LDE3ICsxNjIsOCBAQCBTWU1fQ09ERV9TVEFSVChoYW5kbGVfZXhjZXB0aW9uKQo+PiA+PiAgICAg ICAgUkVHX1MgeDUsICBQVF9UMChzcCkKPj4gPj4gICAgICAgIHNhdmVfZnJvbV94Nl90b194MzEK Pj4gPj4KPj4gPj4tICAgICAgIC8qCj4+ID4+LSAgICAgICAgKiBEaXNhYmxlIHVzZXItbW9kZSBt ZW1vcnkgYWNjZXNzIGFzIGl0IHNob3VsZCBvbmx5IGJlIHNldAo+PiA+PmluIHRoZQo+PiA+Pi0g ICAgICAgICogYWN0dWFsIHVzZXIgY29weSByb3V0aW5lcy4KPj4gPj4tICAgICAgICAqCj4+ID4+ LSAgICAgICAgKiBEaXNhYmxlIHRoZSBGUFUvVmVjdG9yIHRvIGRldGVjdCBpbGxlZ2FsIHVzYWdl IG9mCj4+ID4+ZmxvYXRpbmcgcG9pbnQKPj4gPj4tICAgICAgICAqIG9yIHZlY3RvciBpbiBrZXJu ZWwgc3BhY2UuCj4+ID4+LSAgICAgICAgKi8KPj4gPj4tICAgICAgIGxpIHQwLCBTUl9TVU0gfCBT Ul9GU19WUyB8IFNSX0VMUAo+PiA+Pi0KPj4gPj4gICAgICAgIFJFR19MIHMwLCBUQVNLX1RJX1VT RVJfU1AodHApCj4+ID4+LSAgICAgICBjc3JyYyBzMSwgQ1NSX1NUQVRVUywgdDAKPj4gPj4rICAg ICAgIGNzcnIgczEsIENTUl9TVEFUVVMKPj4gPj4gICAgICAgIHNhdmVfdXNlcnNzcCBzMiwgczEK Pj4gPj4gICAgICAgIGNzcnIgczIsIENTUl9FUEMKPj4gPj4gICAgICAgIGNzcnIgczMsIENTUl9U VkFMCj4+ID4+QEAgLTE4NSw2ICsxNzYsMTYgQEAgU1lNX0NPREVfU1RBUlQoaGFuZGxlX2V4Y2Vw dGlvbikKPj4gPj4gICAgICAgIFJFR19TIHM0LCBQVF9DQVVTRShzcCkKPj4gPj4gICAgICAgIFJF R19TIHM1LCBQVF9UUChzcCkKPj4gPj4KPj4gPj4rICAgICAgIC8qCj4+ID4+KyAgICAgICAgKiBJ dCBpcyBmcmVzaCB0cmFwIGVudHJ5LiBEaXNhYmxlIHVzZXItbW9kZSBtZW1vcnkgYWNjZXNzCj4+ ID4+YXMgaXQgc2hvdWxkIG9ubHkgYmUgc2V0IGluIHRoZQo+PiA+PisgICAgICAgICogYWN0dWFs IHVzZXIgY29weSByb3V0aW5lcy4KPj4gPj4rICAgICAgICAqCj4+ID4+KyAgICAgICAgKiBEaXNh YmxlIHRoZSBGUFUvVmVjdG9yIHRvIGRldGVjdCBpbGxlZ2FsIHVzYWdlIG9mCj4+ID4+ZmxvYXRp bmcgcG9pbnQKPj4gPj4rICAgICAgICAqIG9yIHZlY3RvciBpbiBrZXJuZWwgc3BhY2UuCj4+ID4+ KyAgICAgICAgKi8KPj4gPj4rICAgICAgIGxpIHQwLCBTUl9TVU0gfCBTUl9GU19WUyB8IFNSX0VM UAo+PiA+PisgICAgICAgY3NycmMgczEsIENTUl9TVEFUVVMsIHQwCj4+ID4+Kwo+PiA+PiAgICAg ICAgLyoKPj4gPj4gICAgICAgICAqIFNldCB0aGUgc2NyYXRjaCByZWdpc3RlciB0byAwLCBzbyB0 aGF0IGlmIGEgcmVjdXJzaXZlCj4+ID4+ZXhjZXB0aW9uCj4+ID4+ICAgICAgICAgKiBvY2N1cnMs IHRoZSBleGNlcHRpb24gdmVjdG9yIGtub3dzIGl0IGNhbWUgZnJvbSB0aGUga2VybmVsCj4+ID4+ Cj4+ID4+Cj4+ID4+Cj4+ID4+RHVyaW5nIHRoZSB0aW1lIHNwZW50IGluIGtlcm5lbCBpZiBzZXRz IFNVTSBiaXQgaW4gc3RhdHVzIHRoZW4sIGFib3ZlCj4+ID4+YF9fc3dpdGNoX3RvX3N0YXR1c2Ag d2lsbCBlbnN1cmUgdGhhdCBgc3RhdHVzYCB3aWxsIGdldCBzYXZlZCBmb3IgY3VycmVudAo+PiA+ PnRocmVhZCBhbmQgcmVzdG9yZWQgZm9yIG5leHQgdGhyZWFkLgo+PiA+Pgo+PiA+PkZ1cnRoZXJt b3JlLCBjdXJyZW50IHRyYXAgZW50cnkgY29kZSBjbGVhcnMgRlMvVlMvU1VNIChmb3IgcmlnaHQK Pj4gPj5yZWFzb25zKS4gSXQKPj4gPj5yZXByZXNlbnRzIG5vbi1saW5lYXIgY2hhbmdlIG9mIGNv bnRyb2wgZmxvdyBhbmQgdGh1cyB3aGF0ZXZlciB3aWxsCj4+ID4+ZXhlY3V0ZSBuZXh0Cj4+ID4+ c2hvdWxkbid0IG5lZWQgU1VNL0ZTL1ZTIHVubGVzcyBpdCB3YW50cyB0byBzZXQgaXQpLiBUaGlz IHBhdGNoIHNsaWdodGx5Cj4+ID4+bW9kaWZpZXMgdGhlIGZsb3cgYnkgZmlyc3Qgc2F2aW5nIHRo ZSBgc3RhdHVzYCBvbiB0cmFwIGZyYW1lICh0aHVzCj4+ID4+aWYgcHJldmlvdXMKPj4gPj50cmFw IGZyYW1lIGhhZCBTVU09MSwgaXQgd2lsbCBiZSBzYXZlZCBhbmQgcmVzdG9yZWQpLiBBbmQgdGhl biBpdAo+PiA+PnVuY29uZGl0aW9uYWxseSBjbGVhcnMgdGhlIFNVTS9GUy9WUyB0byBlbnN1cmUg dGhhdCB0aGlzIG5ldyB0cmFwCj4+ID4+Y29udGV4dCBydW5zCj4+ID4+d2l0aG91dCBuZWVkaW5n IFNVTT0xLiBUaGlzIGVuc3VyZXMgbmVzdGluZyBvZiB0cmFwIGZyYW1lcyB3aXRob3V0Cj4+ID4+ ZGlsdXRpbmcKPj4gPj5zZWN1cml0eSBwcm9wZXJ0aWVzIG9mIFNVTS4KPj4gPj4KPj4gPj4+Cj4+ ID4+PlRoYW5rcywKPj4gPj4+QW5keQo+PiA+Pj4KPj4gPj4+Cj4+ID4+Pgo+PiA+Pj4KPj4gPj4+ Pgo+PiA+Pj4+U28gbXkgZmlyc3QgcXVlc3Rpb24gd2FzIHdoeSBub3QgdG8gdXNlIGBzdGF0dXNg IGluIGBwdF9yZWdzYC4KPj4gPj4+Pkl0IGlzIGdyYW51bGFyCj4+ID4+Pj5hcyBpdCBjYW4gZ2V0 IChpdCBpcyBhdmFpbGFibGUgcGVyIHRocmVhZCBjb250ZXh0IHBlciB0cmFwIGJhc2lzKS4KPj4g Pj4+Pgo+PiA+Pj4+Cj4+ID4+Pj5JIGRpZCBhc2sgQWxleCBhcyB3ZWxsLiBJJ2xsIHBpbmcgaGlt IGFnYWluLgo+PiA+Pj4+Cj4+ID4+Pj4+Cj4+ID4+Pj4+RG9lcyBhbnlvbmUgZWxzZSBoYXZlIGFu eSBjb21tZW50IG9uIHRoaXM/Cj4+ID4+Pj4+Cj4+ID4+Pj4+Pgo+PiA+Pj4+Pj4+PiAgICB1MzIg cmlzY3Zfdl9mbGFnczsKPj4gPj4+Pj4+Pj4gICAgdTMyIHZzdGF0ZV9jdHJsOwo+PiA+Pj4+Pj4+ PiAgICBzdHJ1Y3QgX19yaXNjdl92X2V4dF9zdGF0ZSB2c3RhdGU7Cj4+ID4+Pj4+Pj4+ZGlmZiAt LWdpdCBhL2FyY2gvcmlzY3Yva2VybmVsL2FzbS1vZmZzZXRzLmMKPj4gPj4+Pj4+Pj5iL2FyY2gv cmlzY3Yva2VybmVsL2FzbS0gb2Zmc2V0cy5jCj4+ID4+Pj4+Pj4+aW5kZXggMTY0OTA3NTUzMDRl Li45NjljNjViMWZlNDEgMTAwNjQ0Cj4+ID4+Pj4+Pj4+LS0tIGEvYXJjaC9yaXNjdi9rZXJuZWwv YXNtLW9mZnNldHMuYwo+PiA+Pj4+Pj4+PisrKyBiL2FyY2gvcmlzY3Yva2VybmVsL2FzbS1vZmZz ZXRzLmMKPj4gPj4+Pj4+Pj5AQCAtMzQsNiArMzQsNyBAQCB2b2lkIGFzbV9vZmZzZXRzKHZvaWQp Cj4+ID4+Pj4+Pj4+ICAgIE9GRlNFVChUQVNLX1RIUkVBRF9TOSwgdGFza19zdHJ1Y3QsIHRocmVh ZC5zWzldKTsKPj4gPj4+Pj4+Pj4gICAgT0ZGU0VUKFRBU0tfVEhSRUFEX1MxMCwgdGFza19zdHJ1 Y3QsIHRocmVhZC5zWzEwXSk7Cj4+ID4+Pj4+Pj4+ICAgIE9GRlNFVChUQVNLX1RIUkVBRF9TMTEs IHRhc2tfc3RydWN0LCB0aHJlYWQuc1sxMV0pOwo+PiA+Pj4+Pj4KPj4gPj4+Pj4+X19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KPj4gPj4+Pj4+bGludXgtcmlz Y3YgbWFpbGluZyBsaXN0Cj4+ID4+Pj4+PmxpbnV4LXJpc2N2QGxpc3RzLmluZnJhZGVhZC5vcmcK Pj4gPj4+Pj4+aHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51 eC1yaXNjdgo+PiA+Pj4+Pj4KPj4gPj4+Pj4KPj4gPj4+Pj4KPj4gPj4+Pj4tLQo+PiA+Pj4+PkJl biBEb29rcyBodHRwOi8vd3d3LmNvZGV0aGluay5jby51ay8KPj4gPj4+Pj5TZW5pb3IgRW5naW5l ZXIgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIENvZGV0aGluayAtCj4+ID4+Pj5Qcm92 aWRpbmcgR2VuaXVzCj4+ID4+Pj4+Cj4+ID4+Pj4+aHR0cHM6Ly93d3cuY29kZXRoaW5rLmNvLnVr L3ByaXZhY3kuaHRtbAo+PiA+Pj4+Cj4+ID4+Pj5fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fXwo+PiA+Pj4+bGludXgtcmlzY3YgbWFpbGluZyBsaXN0Cj4+ID4+ Pj5saW51eC1yaXNjdkBsaXN0cy5pbmZyYWRlYWQub3JnCj4+ID4+Pj5odHRwOi8vbGlzdHMuaW5m cmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LXJpc2N2Cj4+ID4+Cj4+ID4+X19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KPj4gPj5saW51eC1yaXNj diBtYWlsaW5nIGxpc3QKPj4gPj5saW51eC1yaXNjdkBsaXN0cy5pbmZyYWRlYWQub3JnCj4+ID4+ aHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1yaXNjdgoK X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtcmlz Y3YgbWFpbGluZyBsaXN0CmxpbnV4LXJpc2N2QGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xp c3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1yaXNjdgo= From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9A051FCFEE for ; Tue, 27 May 2025 20:58:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379506; cv=none; b=BmD6a9Ms+ZXfd0hz6PNMMAMsnFCdYGzaxMrZ/vidWqHTL0mJi0Tljkxg9M0ohBFZt+8mDZxE8kQNDvGN2kipyFs5uDTQXR4XdsquV8GVNh71v9hm7gsT3dFx+2XqKTixGyZH7LVCB5qeVtyS/LtKOcUWL4Q/PCVO54+TyL1tgFc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748379506; c=relaxed/simple; bh=6n22yrV1lFp1xH71jk2cjwaJjI/APC7+azXhOHFtEZs=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=VaraX5sHSC+nN5CvHOwTcYpc8Q8EvaoYqplSaWrlDAxttCFYAIrqsPY8fTKNthPxb4RZ2j2uaNpc6fmbtyjx1sc6ZHMwh8o9aDxx1C3nEzJsKrko8SrT0cfee9NLqobLKPIpLEJwC43aZruomdJdWt8ScBsfIixmiELiGnoTLFY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=eJ2dQ65B; arc=none smtp.client-ip=209.85.210.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="eJ2dQ65B" Received: by mail-pf1-f172.google.com with SMTP id d2e1a72fcca58-742b0840d98so2565630b3a.1 for ; Tue, 27 May 2025 13:58:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1748379503; x=1748984303; darn=vger.kernel.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=aNdKSRE+7GllioeuKKKCmHh0OzVPY+Ey8A+JicvvVpc=; b=eJ2dQ65BUL2NdZukf/VSh3V9bb97MUOJR1vKbQMXUuqeV4y2Sl3ic6/ogr5sdUITV/ xp/ZV1WURBiu+uZb57/fI269+55d05JGPNFAaEsoX5/Rtb2Qt936VHRMKsd60ZB8OOX4 jaN/PNHxZ+aemtWRbsOaK9J0djFGGR/Q247RTY0d0MdjSBiZqdlXi5zfN3+q5P5Bg0vI bQLqXKzYZpjnSuUDo2pccbBKJr09r2YuKHFTH9xxSbheGQIwqAXh7MDkai2/otcGsKkI oPOXtO3TMzEyLhUm/2K48vNyU2CzqTlu5XOTYAGWgMLehg82AJQIv3Pz7U8eHwHGdm/p ZV8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748379503; x=1748984303; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=aNdKSRE+7GllioeuKKKCmHh0OzVPY+Ey8A+JicvvVpc=; b=k/QmlvKFrKhsDSFWUyavuEKWmNf7nhmG39kSsE1ChzUBpO58sVN4EyOaHCBjYM3zZP ugwnGkxwSDpRlCQD8n/WUAx+wItMfYDXxVC36Gz8Dl1zloQdqoXnYsPSouZzLl8V7SYc /kI9MBeB3AtHhMQ4R6nja1DI7qoGbMZsUgF2ALrzW8wi3NJOrCXlF/e+/TRJ32xuMtXv qmlLusH3DEZFYEmignXbsdvMswNmo+0ksT9XQM9uZ4EHlyK2G+kXerxC8kJE72lZzpEQ REuaGIyVshVXG34OpLegTOU43BJaMIVOknkjdPAdRQBc6BTi9CS2/HDytyifuwkjkrMr aJ3A== X-Forwarded-Encrypted: i=1; AJvYcCXvmmzX/kZSRa+Pu4fD+ijezL5NaBdMPCx8vzKM6jCac2tb8dwBP7zSI+1Ogvp5auhZRJHofyWijjohARU=@vger.kernel.org X-Gm-Message-State: AOJu0Yxi6BDZGopI9rqs/uB9UX+geCBcXrUDkkWJ3JoVcncPhCvvuqck hMx0N+8YRENDHmm6QvgsMBYffxZQm8SgWzeRqmFDm/+I0rTZqH5t7SZhLHCy085WNkE= X-Gm-Gg: ASbGnctXWWJWC03DYDO5+G5H52OPqEGbYS1+vpnJ1FHOQq2qnBGfR0lH7M9zJIeVrmI 9b8wp/VmcOpcsMyS2W3xoYIWqB9sASdhiVfXtLDjSlPToB91hR+aBK0km95QlYH8inyjnTY3zqc JzlZf6pgY4aNqzyT0XypEHEautPRth+cDAWeJHVjTeKSfuErtpp/8RPLtX5X1Lvpfe1API3y02n fp6vtjj8chQalm03gnEjdr6r26Ar7gWCnkCQhMeReY62hNDEicrUXOR8sp+RsDpk10NdLPPLNb4 KvykGJmUqBAStHChgQwuTPDknjOKMBedzXWt4q090vzw+w6/g1881hz/ueBxrw== X-Google-Smtp-Source: AGHT+IF80NTZE/eApE9Z4200qK9MpmEpuFOgm2Uyz77PLVPr0kED6gBP29OsakUyqzggLqC0QjIHww== X-Received: by 2002:a05:6a20:7d9b:b0:215:f26f:90e9 with SMTP id adf61e73a8af0-2188c299141mr22152343637.22.1748379502952; Tue, 27 May 2025 13:58:22 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74668301bacsm12016b3a.169.2025.05.27.13.58.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 May 2025 13:58:22 -0700 (PDT) Date: Tue, 27 May 2025 13:58:20 -0700 From: Deepak Gupta To: Andy Chiu Cc: Alexandre Ghiti , Ben Dooks , Cyril Bur , palmer@dabbelt.com, aou@eecs.berkeley.edu, paul.walmsley@sifive.com, charlie@rivosinc.com, jrtc27@jrtc27.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, jszhang@kernel.org, syzbot+e74b94fe601ab9552d69@syzkaller.appspotmail.com Subject: Re: [PATCH v6 1/5] riscv: save the SR_SUM status over switches Message-ID: References: <20250410070526.3160847-2-cyrilbur@tenstorrent.com> <54d63ebf-b66f-41d4-85b1-ec0fa3401333@ghiti.fr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Sat, May 24, 2025 at 06:00:00PM +0800, Andy Chiu wrote: >On Sat, May 24, 2025 at 1:14 AM Deepak Gupta wrote: >> >> On Fri, May 23, 2025 at 02:22:21PM +0200, Alexandre Ghiti wrote: >> >Hi Andy, Deepak, >> > >> >On 5/23/25 00:43, Deepak Gupta wrote: >> >>On Fri, May 23, 2025 at 01:42:49AM +0800, Andy Chiu wrote: >> >>>On Thu, May 22, 2025 at 11:09 PM Deepak Gupta >> >>>wrote: >> >>>> >> >>>>On Thu, May 22, 2025 at 07:23:32AM +0100, Ben Dooks wrote: >> >>>>>On 20/05/2025 17:49, Deepak Gupta wrote: >> >>>>>>I did give this patch my RB and had planned to come back to it to see >> >>>>>>if it impacts cfi related patches. Thanks to alex for brinigng to my >> >>>>>>attention again. As it stands today, it doesn't impact cfi related >> >>>>>>changes but I've some concerns. >> >>>>>> >> >>>>>>Overall I do agree we should reduce number of SSTATUS accesses. >> >>>>>> >> >>>>>>Couple of questions on introducing new `sstatus` field (inline) >> >>>>>> >> >>>>>>On Tue, Apr 22, 2025 at 04:01:35PM -0700, Deepak Gupta wrote: >> >>>>>>>On Thu, Apr 10, 2025 at 07:05:22AM +0000, Cyril Bur wrote: >> >>>>>>>>From: Ben Dooks >> >>>>>>>> >> >>>>>>>>When threads/tasks are switched we need to ensure the old >> >>>>execution's >> >>>>>>>>SR_SUM state is saved and the new thread has the old SR_SUM state >> >>>>>>>>restored. >> >>>>>>>> >> >>>>>>>>The issue was seen under heavy load especially with the >> >>>>syz-stress tool >> >>>>>>>>running, with crashes as follows in schedule_tail: >> >>>>>>>> >> >>>>>>>>Unable to handle kernel access to user memory without >> >>>>uaccess routines >> >>>>>>>>at virtual address 000000002749f0d0 >> >>>>>>>>Oops [#1] >> >>>>>>>>Modules linked in: >> >>>>>>>>CPU: 1 PID: 4875 Comm: syz-executor.0 Not tainted >> >>>>>>>>5.12.0-rc2-syzkaller-00467-g0d7588ab9ef9 #0 >> >>>>>>>>Hardware name: riscv-virtio,qemu (DT) >> >>>>>>>>epc : schedule_tail+0x72/0xb2 kernel/sched/core.c:4264 >> >>>>>>>>ra : task_pid_vnr include/linux/sched.h:1421 [inline] >> >>>>>>>>ra : schedule_tail+0x70/0xb2 kernel/sched/core.c:4264 >> >>>>>>>>epc : ffffffe00008c8b0 ra : ffffffe00008c8ae sp : ffffffe025d17ec0 >> >>>>>>>>gp : ffffffe005d25378 tp : ffffffe00f0d0000 t0 : 0000000000000000 >> >>>>>>>>t1 : 0000000000000001 t2 : 00000000000f4240 s0 : ffffffe025d17ee0 >> >>>>>>>>s1 : 000000002749f0d0 a0 : 000000000000002a a1 : 0000000000000003 >> >>>>>>>>a2 : 1ffffffc0cfac500 a3 : ffffffe0000c80cc a4 : 5ae9db91c19bbe00 >> >>>>>>>>a5 : 0000000000000000 a6 : 0000000000f00000 a7 : ffffffe000082eba >> >>>>>>>>s2 : 0000000000040000 s3 : ffffffe00eef96c0 s4 : ffffffe022c77fe0 >> >>>>>>>>s5 : 0000000000004000 s6 : ffffffe067d74e00 s7 : ffffffe067d74850 >> >>>>>>>>s8 : ffffffe067d73e18 s9 : ffffffe067d74e00 s10: ffffffe00eef96e8 >> >>>>>>>>s11: 000000ae6cdf8368 t3 : 5ae9db91c19bbe00 t4 : ffffffc4043cafb2 >> >>>>>>>>t5 : ffffffc4043cafba t6 : 0000000000040000 >> >>>>>>>>status: 0000000000000120 badaddr: 000000002749f0d0 cause: >> >>>>>>>>000000000000000f >> >>>>>>>>Call Trace: >> >>>>>>>>[] schedule_tail+0x72/0xb2 >> >>>>kernel/sched/core.c:4264 >> >>>>>>>>[] ret_from_exception+0x0/0x14 >> >>>>>>>>Dumping ftrace buffer: >> >>>>>>>> (ftrace buffer empty) >> >>>>>>>>---[ end trace b5f8f9231dc87dda ]--- >> >>>>>>>> >> >>>>>>>>The issue comes from the put_user() in schedule_tail >> >>>>>>>>(kernel/sched/core.c) doing the following: >> >>>>>>>> >> >>>>>>>>asmlinkage __visible void schedule_tail(struct task_struct *prev) >> >>>>>>>>{ >> >>>>>>>>... >> >>>>>>>> if (current->set_child_tid) >> >>>>>>>> put_user(task_pid_vnr(current), >> >>>>current->set_child_tid); >> >>>>>>>>... >> >>>>>>>>} >> >>>>>>>> >> >>>>>>>>the put_user() macro causes the code sequence to come out as >> >>>>follows: >> >>>>>>>> >> >>>>>>>>1: __enable_user_access() >> >>>>>>>>2: reg = task_pid_vnr(current); >> >>>>>>>>3: *current->set_child_tid = reg; >> >>>>>>>>4: __disable_user_access() >> >>>>>>>> >> >>>>>>>>The problem is that we may have a sleeping function as >> >>>>argument which >> >>>>>>>>could clear SR_SUM causing the panic above. This was fixed by >> >>>>>>>>evaluating the argument of the put_user() macro outside the >> >>>>user-enabled >> >>>>>>>>section in commit 285a76bb2cf5 ("riscv: evaluate put_user() >> >>>>arg before >> >>>>>>>>enabling user access")" >> >>>>>>>> >> >>>>>>>>In order for riscv to take advantage of unsafe_get/put_XXX() >> >>>>macros and >> >>>>>>>>to avoid the same issue we had with put_user() and sleeping >> >>>>functions we >> >>>>>>>>must ensure code flow can go through switch_to() from within >> >>>>a region of >> >>>>>>>>code with SR_SUM enabled and come back with SR_SUM still >> >>>>enabled. This >> >>>>>>>>patch addresses the problem allowing future work to enable >> >>>>full use of >> >>>>>>>>unsafe_get/put_XXX() macros without needing to take a CSR >> >>>>bit flip cost >> >>>>>>>>on every access. Make switch_to() save and restore SR_SUM. >> >>>>>>>> >> >>>>>>>>Reported-by: syzbot+e74b94fe601ab9552d69@syzkaller.appspotmail.com >> >>>>>>>>Signed-off-by: Ben Dooks >> >>>>>>>>Signed-off-by: Cyril Bur >> >>>>>>>>--- >> >>>>>>>>arch/riscv/include/asm/processor.h | 1 + >> >>>>>>>>arch/riscv/kernel/asm-offsets.c | 5 +++++ >> >>>>>>>>arch/riscv/kernel/entry.S | 8 ++++++++ >> >>>>>>>>3 files changed, 14 insertions(+) >> >>>>>>>> >> >>>>>>>>diff --git a/arch/riscv/include/asm/processor.h >> >>>>>>>>b/arch/riscv/include/ asm/processor.h >> >>>>>>>>index 5f56eb9d114a..58fd11c89fe9 100644 >> >>>>>>>>--- a/arch/riscv/include/asm/processor.h >> >>>>>>>>+++ b/arch/riscv/include/asm/processor.h >> >>>>>>>>@@ -103,6 +103,7 @@ struct thread_struct { >> >>>>>>>> struct __riscv_d_ext_state fstate; >> >>>>>>>> unsigned long bad_cause; >> >>>>>>>> unsigned long envcfg; >> >>>>>>>>+ unsigned long status; >> >>>>>> >> >>>>>>Do we really need a new member field in `thread_struct`. We >> >>>>already have >> >>>>>>`sstatus` in `pt_regs` which reflects overall execution environment >> >>>>>>situation >> >>>>>>for current thread. This gets saved and restored on trap entry >> >>>>and exit. >> >>>>>> >> >>>>>>If we put `status` in `thread_struct` it creates ambiguity in terms >> >>>>>>of which >> >>>>>>`status` to save to and pick from from future maintainibility >> >>>>>>purposes as the >> >>>>>>fields get introduced to this CSR. >> >>>>>> >> >>>>>>Why can't we access current trap frame's `sstatus` image in >> >>>>>>`__switch_to` to >> >>>>>>save and restore? >> >>>>>> >> >>>>>>Let me know if I am missing something obvious here. If there is a >> >>>>>>complication, >> >>>>>>I am missing here and we do end up using this member field, I would >> >>>>>>rename it >> >>>>>>to something like `status_kernel` to reflect that. So that future >> >>>>>>changes are >> >>>>>>cognizant of the fact that we have split `status`. One for kernel >> >>>>>>execution env >> >>>>>>per thread and one for controlling user execution env per thread. >> >>>>> >> >>>>>This is so long ago now I cannot remember if there was any sstatus in >> >>>>>the pt_regs field, >> >>>> >> >>>>FS/VS bits encode status of floating point and vector on >> >>>>per-thread basis. >> >>>>So `status` has been part of `pt_regs` for quite a while. >> >>>> >> >>>>> and if kernel threads have the same context as their >> >>>>>userland parts. >> >>>> >> >>>>I didn't mean kernel thread. What I meant was kernel execution >> >>>>environment >> >>>>per-thread. A userland thread does spend sometime in kernel and >> >>>>kernel does >> >>>>things on its behalf. One of those thing is touching user memory >> >>>>and that >> >>>>requires mucking with this CSR. So what I meant was are we >> >>>>splitting `status` >> >>>>on per-thread basis for their time spent in user and kernel. >> >>>> >> >>>>Getting back to original question-- >> >>>>As I said, each thread spends sometime in user or in kernel. >> >>>>`status` in >> >>>>`pt_regs` is saved on trap entry and restored on trap exit. In a sense, >> >>>>`status` field in `pt_regs` is reflecting execution status of >> >>>>the thread on per >> >>>>trap basis. Introducing `status` in `thread_struct` creates a >> >>>>confusion (if not >> >>>>for today, certainly for future) of which `status` to pick from >> >>>>when we are >> >>>>doing save/restore. >> >>> >> >>>I agree that it's a confusion. sstatus is already saved on pt_regs on >> >>>trap entries/return, adding another entry adds code complexity and >> >>>makes data inconsistent. But, perhaps we'd eventually need something >> >>>like this (I will explain why). Still, there might be a better >> >>>approach. >> >>> >> >>>Yes, we can always reflect pt_regs for sstatus. We all know that >> >>>pt_regs reflects sstatus at trap entry, and the pt_regs at scheduler >> >>>point refers to "user's" pt_regs whenever it first enters kernel >> >>>mode. Here >> >>>are reasons why SR_SUM here may or may not be properly tracked. First, >> >>>if this is a trap introduced context switch (such as interrupting in a >> >>>preemptible context after we manually enable user access in put_user), >> >>>then SR_SUM is saved somewhere in the kernel stack, and is not >> >>>reference-able with task_pt_reg during context switch. But we are safe >> >>>because the trap exit asm would help us restore the correct SR_SUM >> >>>back. However, if this is a self-initiating context switch (calling >> >>>into schedule()), then SR_SUM is not saved anywhere, and possibly >> >>>causing this error. >> >>> >> >>>Preemptible Vector in the kernel mode also had this problem where a >> >>>self-initiating context switch loses the track of sstatus.vs. The way >> >>>I managed it is to track the VS bit at context switch time. However, >> >>>this bug shows that people are repeatedly facing the problem, and >> >>>maybe it suggests that we'd need a better way of managing sstatus >> >>>across context switches. Given the complex nature of this register, >> >>>which also touches the interrupt enable status, I don't think naively >> >>>saving/restoring the entire register is the way to go. Maybe the >> >>>variable deserves a more specific naming and documentation. And if >> >>>we'd need a centralized place for managing these statuses, then it >> >>>also has to take care of sstatus.VS. >> > >> > >> >Andy, thanks for the precise explanation of the problem :) > >Thanks for reading it Alex! It's my bad making it wordy > >> > >> >So it took me some time but here are my thoughts on this. We should >> >treat pt_regs and thread_struct differently as they do not represent >> >the same thing: >> >- pt_regs represents the context of a thread when it takes a trap >> >- thread_struct represents a "kernel-induced" (or a "in-kernel") >> >context not caused by traps >> >> Exactly they represent different context of execution. Trap represents a >> non-linear control flow change and thus a fresh start of execution control >> flow into kernel while `kernel-induced` one's are again non-linear but >> fully a kernel/software construct. >> >> A fresh trapped execution context shouldn't have SUM set which is how it is >> currently in kernel. This bit gets cleared in trap entry and `sstatus` gets >> saved in `pt_regs` (including SR_IE) so that it could be restored whenever >> `sret` happens. >> >> The problem we'are seeing here is two fold-- >> >> 1) We don't want to set and clear when we are accessing array/string for each >> word. This is software problem and this entire series is addressing it. >> >> 2) To avoid first problem we are optimizing the access to CSR by setting it >> once and clearing it once. But now we don't want to loose this bit if there >> were: >> >> a) trap in between >> b) kernel induced schedule out >> c) a) followed by b) >> d) a) followed by another a) >> e) nested traps >> >> If a) occurs, we are definitley loosing the bit as per current code. If b) >> happens then also the same situation. >> >> Saving it in `thread_struct` only addresses `b`. And not `a`, `c`, `d` and >> `e`. IMHO `e` is far-fetched situation but I believe `a`, `b`, `c` and `d` happen >> during normal runtime of kernel. > >The trap entry/exit routine should always take care of trap cases, >whenever the kernel traps, SUM is saved to pt_regs somewhere in the >kernel stack. Yes, a task may be scheduled out after a trap, which is >common, but please be aware of that after scheduling back to the >original task, it then has to execute the trap exit and thus restore >the SUM before going back to the original code (where it receives an >exception). Yes you are right. Thanks for correcting me. As I mentioned in another fork of the thread. The nesting of traps is taken care of by trap entry/exit. It's all about kernel induced event then. Is there nesting of kernel induced event? If there is no nesting then sure a field in `thread_struct` is fine. But then in that case save/restore is in `pt_regs` is also fine and keep a single image which truly represents current context and trap together. > >> >> So it all depends on nesting level of traps supported by riscv kernel. >> >> Illustraing `c + d` example, if kernel can take 2 nested level of traps with >> first trap context having had the SUM bit set, but the second trap had it clear >> and now comes the switch out of this thread, at this point if it were saved in >> `thread_struct` SUM would be lost for the first trap. > >No, the trap exit always restores the in-context (correct) sstatus back > >> >> Later when the thread gets switched in again, you would go in 2nd trap >> context without SUM (because `thread_context` didnt had it saved), which is >> fine. Although when 2nd trap context eventually performs `sret`, it will >> go back to first trap context where SUM was expected to be set because it >> touching a user memory. >> >> A good example would be a syscall, so that's the first trap. SUM bit is set, >> touched user memory and took a trap (page fault). Now code is in second trap >> which should clear the SUM bit. Somewhere in memory manager stack, thread is >> scheduled out and now `sstatus` is saved in `thread_struct`. This is only >> serving current trap context needs and not the one where `SUM` needed to be >> set. >> >> We can support such nesting only by ensuring below >> >> On trap entry do >> - save `status` in `pt_regs` or some other FILO data structure >> - clear SUM (and other bits needed to be cleared) >> >> On trap return do >> - reload `status` from `pt_regs` or some FILO data structure >> >> Quite analogous to what we do for SR_IE as well. > >I am not sure if I understand what FILO is, but the current trap >handling routines do save/restore sstatus, which can be found at >handle_exception and ret_from_exception, as of today. > >> >> > >> >That's why I don't really like Deepak's proposal below as it mixes >> >both and I find it tricky. >> > >> >I can't find a situation where saving/restoring the entire sstatus at >> >context-switch is a problem though, does anyone have such thing in >> >mind? > >I agree that we should keep track of sstatus somewhere and be explicit >about what context it tracks. > >sstatus not just tracks per-thread status, some are machine-wide. >Though __switch_to are always called with interrupt disabled, I think >conceptually interrupt enable status should not be saved/restore on a >per-thread basis. > >Just FYI that some statuses are currently managed by individual >modules (such as the live sstatus.VS are managed in asm/vector.h). We >can discuss what is prefered. The final patch should take care of >this, or should document that VS is managed elsewhere, if we would >like a centralized sstatus management. > >Personally, I would prefer a centralized sstatus management that only >touches SUM. This prevents duplicating condition matchings for vector >out to other places. But maybe there are better ways > >Thanks, >Andy > > > > >> > >> >Finally I understand that having another copy of sstatus in >> >thread_struct is not intuitive and we should, either explain why or >> >only store the SUM bit (like for sstatus.VS). >> > >> >Please continue the discussion as we need to find a solution that >> >pleases everyone soon :) >> > >> >Thanks all for jumping in, >> > >> >Alex >> > >> > >> >> >> >> >> >>IMHO, the problem we are trying to solve in this patch is easily >> >>solvable in >> >>below manner. >> >> >> >> >> >>diff --git a/arch/riscv/include/asm/switch_to.h >> >>b/arch/riscv/include/asm/switch_to.h >> >>index 0e71eb82f920..499d00a6fb67 100644 >> >>--- a/arch/riscv/include/asm/switch_to.h >> >>+++ b/arch/riscv/include/asm/switch_to.h >> >>@@ -58,6 +58,20 @@ static inline void __switch_to_fpu(struct >> >>task_struct *prev, >> >> fstate_restore(next, task_pt_regs(next)); >> >> } >> >> >> >>+static inline void __switch_to_status(struct task_struct *prev, >> >>+ struct task_struct *next) >> >>+{ >> >>+ struct pt_regs *regs; >> >>+ >> >>+ /* save status */ >> >>+ regs = task_pt_regs(prev); >> >>+ regs->status = csr_read(CSR_STATUS); >> >>+ >> >>+ /* restore status */ >> >>+ regs = task_pt_regs(next); >> >>+ csr_write(CSR_STATUS, regs->status); >> >>+} >> >>+ >> >> static __always_inline bool has_fpu(void) >> >> { >> >> return riscv_has_extension_likely(RISCV_ISA_EXT_f) || >> >>@@ -115,6 +129,7 @@ do >> >>{ \ >> >> struct task_struct *__prev = (prev); \ >> >> struct task_struct *__next = (next); \ >> >> __set_prev_cpu(__prev->thread); \ >> >>+ __switch_to_status(__prev, __next) \ >> >> if (has_fpu()) \ >> >> __switch_to_fpu(__prev, __next); \ >> >> if (has_vector() || has_xtheadvector()) \ >> >>diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S >> >>index 8d25837a9384..a3b98c1be055 100644 >> >>--- a/arch/riscv/kernel/entry.S >> >>+++ b/arch/riscv/kernel/entry.S >> >>@@ -162,17 +162,8 @@ SYM_CODE_START(handle_exception) >> >> REG_S x5, PT_T0(sp) >> >> save_from_x6_to_x31 >> >> >> >>- /* >> >>- * Disable user-mode memory access as it should only be set >> >>in the >> >>- * actual user copy routines. >> >>- * >> >>- * Disable the FPU/Vector to detect illegal usage of >> >>floating point >> >>- * or vector in kernel space. >> >>- */ >> >>- li t0, SR_SUM | SR_FS_VS | SR_ELP >> >>- >> >> REG_L s0, TASK_TI_USER_SP(tp) >> >>- csrrc s1, CSR_STATUS, t0 >> >>+ csrr s1, CSR_STATUS >> >> save_userssp s2, s1 >> >> csrr s2, CSR_EPC >> >> csrr s3, CSR_TVAL >> >>@@ -185,6 +176,16 @@ SYM_CODE_START(handle_exception) >> >> REG_S s4, PT_CAUSE(sp) >> >> REG_S s5, PT_TP(sp) >> >> >> >>+ /* >> >>+ * It is fresh trap entry. Disable user-mode memory access >> >>as it should only be set in the >> >>+ * actual user copy routines. >> >>+ * >> >>+ * Disable the FPU/Vector to detect illegal usage of >> >>floating point >> >>+ * or vector in kernel space. >> >>+ */ >> >>+ li t0, SR_SUM | SR_FS_VS | SR_ELP >> >>+ csrrc s1, CSR_STATUS, t0 >> >>+ >> >> /* >> >> * Set the scratch register to 0, so that if a recursive >> >>exception >> >> * occurs, the exception vector knows it came from the kernel >> >> >> >> >> >> >> >>During the time spent in kernel if sets SUM bit in status then, above >> >>`__switch_to_status` will ensure that `status` will get saved for current >> >>thread and restored for next thread. >> >> >> >>Furthermore, current trap entry code clears FS/VS/SUM (for right >> >>reasons). It >> >>represents non-linear change of control flow and thus whatever will >> >>execute next >> >>shouldn't need SUM/FS/VS unless it wants to set it). This patch slightly >> >>modifies the flow by first saving the `status` on trap frame (thus >> >>if previous >> >>trap frame had SUM=1, it will be saved and restored). And then it >> >>unconditionally clears the SUM/FS/VS to ensure that this new trap >> >>context runs >> >>without needing SUM=1. This ensures nesting of trap frames without >> >>diluting >> >>security properties of SUM. >> >> >> >>> >> >>>Thanks, >> >>>Andy >> >>> >> >>> >> >>> >> >>> >> >>>> >> >>>>So my first question was why not to use `status` in `pt_regs`. >> >>>>It is granular >> >>>>as it can get (it is available per thread context per trap basis). >> >>>> >> >>>> >> >>>>I did ask Alex as well. I'll ping him again. >> >>>> >> >>>>> >> >>>>>Does anyone else have any comment on this? >> >>>>> >> >>>>>> >> >>>>>>>> u32 riscv_v_flags; >> >>>>>>>> u32 vstate_ctrl; >> >>>>>>>> struct __riscv_v_ext_state vstate; >> >>>>>>>>diff --git a/arch/riscv/kernel/asm-offsets.c >> >>>>>>>>b/arch/riscv/kernel/asm- offsets.c >> >>>>>>>>index 16490755304e..969c65b1fe41 100644 >> >>>>>>>>--- a/arch/riscv/kernel/asm-offsets.c >> >>>>>>>>+++ b/arch/riscv/kernel/asm-offsets.c >> >>>>>>>>@@ -34,6 +34,7 @@ void asm_offsets(void) >> >>>>>>>> OFFSET(TASK_THREAD_S9, task_struct, thread.s[9]); >> >>>>>>>> OFFSET(TASK_THREAD_S10, task_struct, thread.s[10]); >> >>>>>>>> OFFSET(TASK_THREAD_S11, task_struct, thread.s[11]); >> >>>>>> >> >>>>>>_______________________________________________ >> >>>>>>linux-riscv mailing list >> >>>>>>linux-riscv@lists.infradead.org >> >>>>>>http://lists.infradead.org/mailman/listinfo/linux-riscv >> >>>>>> >> >>>>> >> >>>>> >> >>>>>-- >> >>>>>Ben Dooks http://www.codethink.co.uk/ >> >>>>>Senior Engineer Codethink - >> >>>>Providing Genius >> >>>>> >> >>>>>https://www.codethink.co.uk/privacy.html >> >>>> >> >>>>_______________________________________________ >> >>>>linux-riscv mailing list >> >>>>linux-riscv@lists.infradead.org >> >>>>http://lists.infradead.org/mailman/listinfo/linux-riscv >> >> >> >>_______________________________________________ >> >>linux-riscv mailing list >> >>linux-riscv@lists.infradead.org >> >>http://lists.infradead.org/mailman/listinfo/linux-riscv