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Fri, 06 Jun 2025 10:30:51 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7482b0836d4sm1517910b3a.85.2025.06.06.10.30.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 10:30:50 -0700 (PDT) Date: Fri, 6 Jun 2025 10:30:48 -0700 From: Deepak Gupta To: Chunyan Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Morton , Alexandre Ghiti , Ved Shanbhogue , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Chunyan Zhang Subject: Re: [PATCH RFC v7 3/3] riscv: mm: Add uffd write-protect support Message-ID: References: <20250409095320.224100-1-zhangchunyan@iscas.ac.cn> <20250409095320.224100-4-zhangchunyan@iscas.ac.cn> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250409095320.224100-4-zhangchunyan@iscas.ac.cn> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250606_103052_072104_ADB12480 X-CRM114-Status: GOOD ( 14.05 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Wed, Apr 09, 2025 at 05:53:20PM +0800, Chunyan Zhang wrote: >The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59 >for software, this patch uses bit 60 for uffd-wp tracking > >Additionally for tracking the uffd-wp state as a PTE swap bit, we borrow >bit 4 which is not involved into swap entry computation. > >Signed-off-by: Chunyan Zhang >--- > arch/riscv/Kconfig | 1 + > arch/riscv/include/asm/pgtable-bits.h | 18 ++++++++ > arch/riscv/include/asm/pgtable.h | 65 +++++++++++++++++++++++++++ > 3 files changed, 84 insertions(+) > >diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >index 652e2bbfb702..cafdfbe4412b 100644 >--- a/arch/riscv/Kconfig >+++ b/arch/riscv/Kconfig >@@ -145,6 +145,7 @@ config RISCV > select HAVE_ARCH_TRACEHOOK > select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT && MMU > select HAVE_ARCH_USERFAULTFD_MINOR if 64BIT && USERFAULTFD >+ select HAVE_ARCH_USERFAULTFD_WP if 64BIT && MMU && USERFAULTFD && RISCV_ISA_SVRSW60T59B > select HAVE_ARCH_VMAP_STACK if MMU && 64BIT > select HAVE_ASM_MODVERSIONS > select HAVE_CONTEXT_TRACKING_USER >diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h >index a6fa871dc19e..a953a582cd75 100644 >--- a/arch/riscv/include/asm/pgtable-bits.h >+++ b/arch/riscv/include/asm/pgtable-bits.h >@@ -39,6 +39,24 @@ > #define _PAGE_SWP_SOFT_DIRTY 0 > #endif /* CONFIG_MEM_SOFT_DIRTY */ > >+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP >+ >+/* ext_svrsw60t59b: Bit(60) for uffd-wp tracking */ >+#define _PAGE_UFFD_WP \ >+ ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ? \ >+ (1UL << 60) : 0) >+/* >+ * Bit 4 is not involved into swap entry computation, so we >+ * can borrow it for swap page uffd-wp tracking. >+ */ >+#define _PAGE_SWP_UFFD_WP \ >+ ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ? \ >+ _PAGE_USER : 0) >+#else >+#define _PAGE_UFFD_WP 0 >+#define _PAGE_SWP_UFFD_WP 0 >+#endif >+ Same comment as previous patch on above. Have `RISCV_ISA_EXT_SVRSW60T59B` with the "#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP" > #define _PAGE_TABLE _PAGE_PRESENT > > /* >diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h >index 14461ffe6321..ee0fbca28a76 100644 >--- a/arch/riscv/include/asm/pgtable.h >+++ b/arch/riscv/include/asm/pgtable.h >@@ -425,6 +425,38 @@ static inline pte_t pte_wrprotect(pte_t pte) > return __pte(pte_val(pte) & ~(_PAGE_WRITE)); > } > >+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP >+static inline bool pte_uffd_wp(pte_t pte) >+{ >+ return !!(pte_val(pte) & _PAGE_UFFD_WP); >+} >+ >+static inline pte_t pte_mkuffd_wp(pte_t pte) >+{ >+ return pte_wrprotect(__pte(pte_val(pte) | _PAGE_UFFD_WP)); >+} >+ >+static inline pte_t pte_clear_uffd_wp(pte_t pte) >+{ >+ return __pte(pte_val(pte) & ~(_PAGE_UFFD_WP)); >+} >+ >+static inline bool pte_swp_uffd_wp(pte_t pte) >+{ >+ return !!(pte_val(pte) & _PAGE_SWP_UFFD_WP); >+} >+ >+static inline pte_t pte_swp_mkuffd_wp(pte_t pte) >+{ >+ return __pte(pte_val(pte) | _PAGE_SWP_UFFD_WP); >+} >+ >+static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) >+{ >+ return __pte(pte_val(pte) & ~(_PAGE_SWP_UFFD_WP)); >+} >+#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ >+ > /* static inline pte_t pte_mkread(pte_t pte) */ > > static inline pte_t pte_mkwrite_novma(pte_t pte) >@@ -853,6 +885,38 @@ static inline pud_t pud_mkspecial(pud_t pud) > } > #endif > >+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP >+static inline bool pmd_uffd_wp(pmd_t pmd) >+{ >+ return pte_uffd_wp(pmd_pte(pmd)); >+} >+ >+static inline pmd_t pmd_mkuffd_wp(pmd_t pmd) >+{ >+ return pte_pmd(pte_mkuffd_wp(pmd_pte(pmd))); >+} >+ >+static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd) >+{ >+ return pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd))); >+} >+ >+static inline bool pmd_swp_uffd_wp(pmd_t pmd) >+{ >+ return pte_swp_uffd_wp(pmd_pte(pmd)); >+} >+ >+static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd) >+{ >+ return pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd))); >+} >+ >+static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd) >+{ >+ return pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd))); >+} >+#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ >+ > #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY > static inline bool pmd_soft_dirty(pmd_t pmd) > { >@@ -978,6 +1042,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, > * bit 0: _PAGE_PRESENT (zero) > * bit 1 to 2: (zero) > * bit 3: _PAGE_SWP_SOFT_DIRTY >+ * bit 4: _PAGE_SWP_UFFD_WP > * bit 5: _PAGE_PROT_NONE (zero) > * bit 6: exclusive marker > * bits 7 to 11: swap type >-- >2.34.1 > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7ABB289E3F for ; Fri, 6 Jun 2025 17:30:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.182 ARC-Seal:i=1; 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Fri, 06 Jun 2025 10:30:51 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7482b0836d4sm1517910b3a.85.2025.06.06.10.30.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jun 2025 10:30:50 -0700 (PDT) Date: Fri, 6 Jun 2025 10:30:48 -0700 From: Deepak Gupta To: Chunyan Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrew Morton , Alexandre Ghiti , Ved Shanbhogue , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Chunyan Zhang Subject: Re: [PATCH RFC v7 3/3] riscv: mm: Add uffd write-protect support Message-ID: References: <20250409095320.224100-1-zhangchunyan@iscas.ac.cn> <20250409095320.224100-4-zhangchunyan@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <20250409095320.224100-4-zhangchunyan@iscas.ac.cn> On Wed, Apr 09, 2025 at 05:53:20PM +0800, Chunyan Zhang wrote: >The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59 >for software, this patch uses bit 60 for uffd-wp tracking > >Additionally for tracking the uffd-wp state as a PTE swap bit, we borrow >bit 4 which is not involved into swap entry computation. > >Signed-off-by: Chunyan Zhang >--- > arch/riscv/Kconfig | 1 + > arch/riscv/include/asm/pgtable-bits.h | 18 ++++++++ > arch/riscv/include/asm/pgtable.h | 65 +++++++++++++++++++++++++++ > 3 files changed, 84 insertions(+) > >diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >index 652e2bbfb702..cafdfbe4412b 100644 >--- a/arch/riscv/Kconfig >+++ b/arch/riscv/Kconfig >@@ -145,6 +145,7 @@ config RISCV > select HAVE_ARCH_TRACEHOOK > select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT && MMU > select HAVE_ARCH_USERFAULTFD_MINOR if 64BIT && USERFAULTFD >+ select HAVE_ARCH_USERFAULTFD_WP if 64BIT && MMU && USERFAULTFD && RISCV_ISA_SVRSW60T59B > select HAVE_ARCH_VMAP_STACK if MMU && 64BIT > select HAVE_ASM_MODVERSIONS > select HAVE_CONTEXT_TRACKING_USER >diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h >index a6fa871dc19e..a953a582cd75 100644 >--- a/arch/riscv/include/asm/pgtable-bits.h >+++ b/arch/riscv/include/asm/pgtable-bits.h >@@ -39,6 +39,24 @@ > #define _PAGE_SWP_SOFT_DIRTY 0 > #endif /* CONFIG_MEM_SOFT_DIRTY */ > >+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP >+ >+/* ext_svrsw60t59b: Bit(60) for uffd-wp tracking */ >+#define _PAGE_UFFD_WP \ >+ ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ? \ >+ (1UL << 60) : 0) >+/* >+ * Bit 4 is not involved into swap entry computation, so we >+ * can borrow it for swap page uffd-wp tracking. >+ */ >+#define _PAGE_SWP_UFFD_WP \ >+ ((riscv_has_extension_unlikely(RISCV_ISA_EXT_SVRSW60T59B)) ? \ >+ _PAGE_USER : 0) >+#else >+#define _PAGE_UFFD_WP 0 >+#define _PAGE_SWP_UFFD_WP 0 >+#endif >+ Same comment as previous patch on above. Have `RISCV_ISA_EXT_SVRSW60T59B` with the "#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP" > #define _PAGE_TABLE _PAGE_PRESENT > > /* >diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h >index 14461ffe6321..ee0fbca28a76 100644 >--- a/arch/riscv/include/asm/pgtable.h >+++ b/arch/riscv/include/asm/pgtable.h >@@ -425,6 +425,38 @@ static inline pte_t pte_wrprotect(pte_t pte) > return __pte(pte_val(pte) & ~(_PAGE_WRITE)); > } > >+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP >+static inline bool pte_uffd_wp(pte_t pte) >+{ >+ return !!(pte_val(pte) & _PAGE_UFFD_WP); >+} >+ >+static inline pte_t pte_mkuffd_wp(pte_t pte) >+{ >+ return pte_wrprotect(__pte(pte_val(pte) | _PAGE_UFFD_WP)); >+} >+ >+static inline pte_t pte_clear_uffd_wp(pte_t pte) >+{ >+ return __pte(pte_val(pte) & ~(_PAGE_UFFD_WP)); >+} >+ >+static inline bool pte_swp_uffd_wp(pte_t pte) >+{ >+ return !!(pte_val(pte) & _PAGE_SWP_UFFD_WP); >+} >+ >+static inline pte_t pte_swp_mkuffd_wp(pte_t pte) >+{ >+ return __pte(pte_val(pte) | _PAGE_SWP_UFFD_WP); >+} >+ >+static inline pte_t pte_swp_clear_uffd_wp(pte_t pte) >+{ >+ return __pte(pte_val(pte) & ~(_PAGE_SWP_UFFD_WP)); >+} >+#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ >+ > /* static inline pte_t pte_mkread(pte_t pte) */ > > static inline pte_t pte_mkwrite_novma(pte_t pte) >@@ -853,6 +885,38 @@ static inline pud_t pud_mkspecial(pud_t pud) > } > #endif > >+#ifdef CONFIG_HAVE_ARCH_USERFAULTFD_WP >+static inline bool pmd_uffd_wp(pmd_t pmd) >+{ >+ return pte_uffd_wp(pmd_pte(pmd)); >+} >+ >+static inline pmd_t pmd_mkuffd_wp(pmd_t pmd) >+{ >+ return pte_pmd(pte_mkuffd_wp(pmd_pte(pmd))); >+} >+ >+static inline pmd_t pmd_clear_uffd_wp(pmd_t pmd) >+{ >+ return pte_pmd(pte_clear_uffd_wp(pmd_pte(pmd))); >+} >+ >+static inline bool pmd_swp_uffd_wp(pmd_t pmd) >+{ >+ return pte_swp_uffd_wp(pmd_pte(pmd)); >+} >+ >+static inline pmd_t pmd_swp_mkuffd_wp(pmd_t pmd) >+{ >+ return pte_pmd(pte_swp_mkuffd_wp(pmd_pte(pmd))); >+} >+ >+static inline pmd_t pmd_swp_clear_uffd_wp(pmd_t pmd) >+{ >+ return pte_pmd(pte_swp_clear_uffd_wp(pmd_pte(pmd))); >+} >+#endif /* CONFIG_HAVE_ARCH_USERFAULTFD_WP */ >+ > #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY > static inline bool pmd_soft_dirty(pmd_t pmd) > { >@@ -978,6 +1042,7 @@ extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma, > * bit 0: _PAGE_PRESENT (zero) > * bit 1 to 2: (zero) > * bit 3: _PAGE_SWP_SOFT_DIRTY >+ * bit 4: _PAGE_SWP_UFFD_WP > * bit 5: _PAGE_PROT_NONE (zero) > * bit 6: exclusive marker > * bits 7 to 11: swap type >-- >2.34.1 >