From: Sean Christopherson <seanjc@google.com>
To: "H. Peter Anvin" <hpa@zytor.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Lai Jiangshan <jiangshanlai@gmail.com>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
Lai Jiangshan <laijs@linux.alibaba.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>,
Joerg Roedel <joro@8bytes.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org
Subject: Re: [PATCH] KVM: X86: Raise #GP when clearing CR0_PG in 64 bit mode
Date: Mon, 9 Jun 2025 07:23:06 -0700 [thread overview]
Message-ID: <aEbuSmAf4aAHztwC@google.com> (raw)
In-Reply-To: <4a66adfa-fc10-4668-9986-55f6cf231988@zytor.com>
On Fri, Jun 06, 2025, H. Peter Anvin wrote:
> On 2021-12-09 09:55, Paolo Bonzini wrote:
> > On 12/7/21 10:52, Lai Jiangshan wrote:
> > > From: Lai Jiangshan <laijs@linux.alibaba.com>
> > >
> > > In the SDM:
> > > If the logical processor is in 64-bit mode or if CR4.PCIDE = 1, an
> > > attempt to clear CR0.PG causes a general-protection exception (#GP).
> > > Software should transition to compatibility mode and clear CR4.PCIDE
> > > before attempting to disable paging.
> > >
> > > Signed-off-by: Lai Jiangshan <laijs@linux.alibaba.com>
> > > ---
> > > arch/x86/kvm/x86.c | 3 ++-
> > > 1 file changed, 2 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> > > index 00f5b2b82909..78c40ac3b197 100644
> > > --- a/arch/x86/kvm/x86.c
> > > +++ b/arch/x86/kvm/x86.c
> > > @@ -906,7 +906,8 @@ int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned
> > > long cr0)
> > > !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
> > > return 1;
> > > - if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
> > > + if (!(cr0 & X86_CR0_PG) &&
> > > + (is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu,
> > > X86_CR4_PCIDE)))
> > > return 1;
> > > static_call(kvm_x86_set_cr0)(vcpu, cr0);
> > >
> >
> > Queued, thanks.
> >
>
> Have you actually checked to see what real CPUs do in this case?
I have now, and EMR at least behaves as the SDM describes. Why do you ask?
kvm_intel: Clearing CR0.PG faulted (vector = 13)
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index f79604bc0127..f90ad464ab7e 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -8637,6 +8637,23 @@ void vmx_exit(void)
kvm_x86_vendor_exit();
}
+static noinline void vmx_disable_paging(void)
+{
+ unsigned long cr0 = native_read_cr0();
+ long vector = -1;
+
+ asm volatile("1: mov %1, %%cr0\n\t"
+ " mov %2, %%cr0\n\t"
+ "2:"
+ _ASM_EXTABLE_FAULT(1b, 2b)
+ : "+a" (vector)
+ : "r" (cr0 & ~X86_CR0_PG), "r" (cr0)
+ : "cc", "memory" );
+
+ pr_warn("Clearing CR0.PG %s (vector = %ld)\n",
+ vector < 0 ? "succeeded" : "faulted", vector);
+}
+
int __init vmx_init(void)
{
int r, cpu;
@@ -8644,6 +8661,8 @@ int __init vmx_init(void)
if (!kvm_is_vmx_supported())
return -EOPNOTSUPP;
+ vmx_disable_paging();
+
/*
* Note, hv_init_evmcs() touches only VMX knobs, i.e. there's nothing
* to unwind if a later step fails.
next prev parent reply other threads:[~2025-06-09 14:23 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-07 9:52 [PATCH] KVM: X86: Raise #GP when clearing CR0_PG in 64 bit mode Lai Jiangshan
2021-12-09 17:55 ` Paolo Bonzini
2025-06-07 0:58 ` H. Peter Anvin
2025-06-09 14:23 ` Sean Christopherson [this message]
2025-06-09 18:16 ` Jim Mattson
2025-06-09 18:20 ` Jim Mattson
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