From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: "Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Jassi Brar" <jassisinghbrar@gmail.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Bartosz Golaszewski" <brgl@bgdev.pl>,
"Uwe Kleine-König" <ukleinek@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Len Brown" <lenb@kernel.org>,
"Sunil V L" <sunilvl@ventanamicro.com>,
"Rahul Pathak" <rpathak@ventanamicro.com>,
"Leyfoon Tan" <leyfoon.tan@starfivetech.com>,
"Atish Patra" <atish.patra@linux.dev>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Anup Patel" <anup@brainfault.org>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 07/23] mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver
Date: Mon, 9 Jun 2025 23:04:24 +0300 [thread overview]
Message-ID: <aEc-SHvL187xdj-m@smile.fi.intel.com> (raw)
In-Reply-To: <CAK9=C2XJwgsC5AK-eVOHQqN1tPxtrsTjVoKdHgALbREv=sb8zQ@mail.gmail.com>
On Mon, Jun 09, 2025 at 05:59:40PM +0530, Anup Patel wrote:
> On Wed, May 28, 2025 at 4:23 PM Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
> > On Sun, May 25, 2025 at 02:16:54PM +0530, Anup Patel wrote:
...
> > > +#include <asm/sbi.h>
> >
> > asm/* usually goes after generic linux/* ones. Why here?
>
> I am not aware of any such convention but I will update anyway.
It's just a common sense. We include most generic first and most custom at
last.
...
> > > +static int mpxy_write_attrs(u32 channel_id, u32 base_attrid, u32 attr_count,
> > > + u32 *attrs_buf)
> > > +{
> > > + struct mpxy_local *mpxy = this_cpu_ptr(&mpxy_local);
> > > + struct sbiret sret;
> > > + u32 i;
> > > +
> > > + if (!mpxy->shmem_active)
> > > + return -ENODEV;
> > > + if (!attr_count || !attrs_buf)
> > > + return -EINVAL;
> > > +
> > > + get_cpu();
> > > +
> > > + for (i = 0; i < attr_count; i++)
> > > + ((__le32 *)mpxy->shmem)[i] = cpu_to_le32(attrs_buf[i]);
> >
> > Don't we have helpers for this? They are suffixed with _array.
> > https://elixir.bootlin.com/linux/v6.15-rc6/source/include/linux/byteorder/generic.h#L168
> > Don't forget to have asm/byteorder.h being included.
> >
> > Ditto for the similar case(s).
>
> The cpu_to_le32_array() and le32_to_cpu_array() helpers update data
> in-place but over here we have separate source and destination.
Fair enough. Perhaps add something like memcpy_to_le32() / memcpy_from_le32()
or alike for your case?
> > > + sret = sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_WRITE_ATTRS,
> > > + channel_id, base_attrid, attr_count, 0, 0, 0);
> > > +
> > > + put_cpu();
> > > + return sbi_err_map_linux_errno(sret.error);
> > > +}
...
> > > + sizeof(mchan->rpmi_attrs) / sizeof(u32),
> > > + (u32 *)&mchan->rpmi_attrs);
> >
> > Why casting? What about alignment?
>
> The RPMI attributes (aka struct sbi_mpxy_rpmi_channel_attrs) are
> a collection of u32 attributes hence we can also treat rpmi_attrs
> as a u32 array. Further, the rpmi_attrs is XLEN aligned within the
> struct mpxy_mbox_channel so no alignment issue with the casting
> on both RV32 and RV64.
>
> If we want to avoid the casting then we will have to use a temporary
> u32 array plus additional memcpy().
OK.
...
> > > + if (mbox->msi_count)
> >
> > Is this check really needed?
>
> MSIs are optional for the SBI MPXY mailbox so we should only use
> platform_device_msi_xyz() APIs only when MSIs are available.
> > > + platform_device_msi_free_irqs_all(mbox->dev);
Hmm... I am not sure why. Do you have any Oops or warnings if the check
is not there and no MSI provided?
> > > +}
--
With Best Regards,
Andy Shevchenko
WARNING: multiple messages have this Message-ID (diff)
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Anup Patel <apatel@ventanamicro.com>
Cc: "Jassi Brar" <jassisinghbrar@gmail.com>,
"Atish Patra" <atish.patra@linux.dev>,
"Michael Turquette" <mturquette@baylibre.com>,
"Uwe Kleine-König" <ukleinek@kernel.org>,
linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org,
"Rob Herring" <robh@kernel.org>,
"Anup Patel" <anup@brainfault.org>,
"Bartosz Golaszewski" <brgl@bgdev.pl>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
devicetree@vger.kernel.org, "Conor Dooley" <conor+dt@kernel.org>,
"Leyfoon Tan" <leyfoon.tan@starfivetech.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Mika Westerberg" <mika.westerberg@linux.intel.com>,
"Stephen Boyd" <sboyd@kernel.org>,
linux-kernel@vger.kernel.org,
"Samuel Holland" <samuel.holland@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Rahul Pathak" <rpathak@ventanamicro.com>,
"Len Brown" <lenb@kernel.org>
Subject: Re: [PATCH v4 07/23] mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver
Date: Mon, 9 Jun 2025 23:04:24 +0300 [thread overview]
Message-ID: <aEc-SHvL187xdj-m@smile.fi.intel.com> (raw)
In-Reply-To: <CAK9=C2XJwgsC5AK-eVOHQqN1tPxtrsTjVoKdHgALbREv=sb8zQ@mail.gmail.com>
On Mon, Jun 09, 2025 at 05:59:40PM +0530, Anup Patel wrote:
> On Wed, May 28, 2025 at 4:23 PM Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
> > On Sun, May 25, 2025 at 02:16:54PM +0530, Anup Patel wrote:
...
> > > +#include <asm/sbi.h>
> >
> > asm/* usually goes after generic linux/* ones. Why here?
>
> I am not aware of any such convention but I will update anyway.
It's just a common sense. We include most generic first and most custom at
last.
...
> > > +static int mpxy_write_attrs(u32 channel_id, u32 base_attrid, u32 attr_count,
> > > + u32 *attrs_buf)
> > > +{
> > > + struct mpxy_local *mpxy = this_cpu_ptr(&mpxy_local);
> > > + struct sbiret sret;
> > > + u32 i;
> > > +
> > > + if (!mpxy->shmem_active)
> > > + return -ENODEV;
> > > + if (!attr_count || !attrs_buf)
> > > + return -EINVAL;
> > > +
> > > + get_cpu();
> > > +
> > > + for (i = 0; i < attr_count; i++)
> > > + ((__le32 *)mpxy->shmem)[i] = cpu_to_le32(attrs_buf[i]);
> >
> > Don't we have helpers for this? They are suffixed with _array.
> > https://elixir.bootlin.com/linux/v6.15-rc6/source/include/linux/byteorder/generic.h#L168
> > Don't forget to have asm/byteorder.h being included.
> >
> > Ditto for the similar case(s).
>
> The cpu_to_le32_array() and le32_to_cpu_array() helpers update data
> in-place but over here we have separate source and destination.
Fair enough. Perhaps add something like memcpy_to_le32() / memcpy_from_le32()
or alike for your case?
> > > + sret = sbi_ecall(SBI_EXT_MPXY, SBI_EXT_MPXY_WRITE_ATTRS,
> > > + channel_id, base_attrid, attr_count, 0, 0, 0);
> > > +
> > > + put_cpu();
> > > + return sbi_err_map_linux_errno(sret.error);
> > > +}
...
> > > + sizeof(mchan->rpmi_attrs) / sizeof(u32),
> > > + (u32 *)&mchan->rpmi_attrs);
> >
> > Why casting? What about alignment?
>
> The RPMI attributes (aka struct sbi_mpxy_rpmi_channel_attrs) are
> a collection of u32 attributes hence we can also treat rpmi_attrs
> as a u32 array. Further, the rpmi_attrs is XLEN aligned within the
> struct mpxy_mbox_channel so no alignment issue with the casting
> on both RV32 and RV64.
>
> If we want to avoid the casting then we will have to use a temporary
> u32 array plus additional memcpy().
OK.
...
> > > + if (mbox->msi_count)
> >
> > Is this check really needed?
>
> MSIs are optional for the SBI MPXY mailbox so we should only use
> platform_device_msi_xyz() APIs only when MSIs are available.
> > > + platform_device_msi_free_irqs_all(mbox->dev);
Hmm... I am not sure why. Do you have any Oops or warnings if the check
is not there and no MSI provided?
> > > +}
--
With Best Regards,
Andy Shevchenko
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linux-riscv mailing list
linux-riscv@lists.infradead.org
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next prev parent reply other threads:[~2025-06-09 20:04 UTC|newest]
Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-25 8:46 [PATCH v4 00/23] Linux SBI MPXY and RPMI drivers Anup Patel
2025-05-25 8:46 ` Anup Patel
2025-05-25 8:46 ` [PATCH v4 01/23] riscv: Add new error codes defined by SBI v3.0 Anup Patel
2025-05-25 8:46 ` Anup Patel
2025-06-06 23:51 ` Atish Patra
2025-06-06 23:51 ` Atish Patra
2025-06-09 5:58 ` Anup Patel
2025-06-09 5:58 ` Anup Patel
2025-05-25 8:46 ` [PATCH v4 02/23] dt-bindings: mailbox: Add bindings for RPMI shared memory transport Anup Patel
2025-05-25 8:46 ` Anup Patel
2025-05-25 8:46 ` [PATCH v4 03/23] dt-bindings: mailbox: Add bindings for RISC-V SBI MPXY extension Anup Patel
2025-05-25 8:46 ` Anup Patel
2025-05-25 8:46 ` [PATCH v4 04/23] RISC-V: Add defines for the SBI message proxy extension Anup Patel
2025-05-25 8:46 ` Anup Patel
2025-05-27 8:47 ` Andy Shevchenko
2025-05-27 8:47 ` Andy Shevchenko
2025-06-09 6:12 ` Anup Patel
2025-06-09 6:12 ` Anup Patel
2025-05-25 8:46 ` [PATCH v4 05/23] mailbox: Add common header for RPMI messages sent via mailbox Anup Patel
2025-05-25 8:46 ` Anup Patel
2025-05-27 11:16 ` Andy Shevchenko
2025-05-27 11:16 ` Andy Shevchenko
2025-06-09 8:48 ` Anup Patel
2025-06-09 8:48 ` Anup Patel
2025-05-25 8:46 ` [PATCH v4 06/23] mailbox: Allow controller specific mapping using fwnode Anup Patel
2025-05-25 8:46 ` Anup Patel
2025-05-27 11:41 ` Andy Shevchenko
2025-05-27 11:41 ` Andy Shevchenko
2025-06-09 9:10 ` Anup Patel
2025-06-09 9:10 ` Anup Patel
2025-06-09 19:53 ` Andy Shevchenko
2025-06-09 19:53 ` Andy Shevchenko
2025-05-25 8:46 ` [PATCH v4 07/23] mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver Anup Patel
2025-05-25 8:46 ` Anup Patel
2025-05-28 10:52 ` Andy Shevchenko
2025-05-28 10:52 ` Andy Shevchenko
2025-06-09 12:29 ` Anup Patel
2025-06-09 12:29 ` Anup Patel
2025-06-09 20:04 ` Andy Shevchenko [this message]
2025-06-09 20:04 ` Andy Shevchenko
2025-06-10 4:35 ` Anup Patel
2025-06-10 4:35 ` Anup Patel
2025-06-10 9:55 ` Andy Shevchenko
2025-06-10 9:55 ` Andy Shevchenko
2025-06-11 5:21 ` Anup Patel
2025-06-11 5:21 ` Anup Patel
2025-06-11 8:23 ` Andy Shevchenko
2025-06-11 8:23 ` Andy Shevchenko
2025-05-25 8:46 ` [PATCH v4 08/23] dt-bindings: clock: Add RPMI clock service message proxy bindings Anup Patel
2025-05-25 8:46 ` Anup Patel
2025-05-30 16:28 ` Conor Dooley
2025-05-30 16:28 ` Conor Dooley
2025-06-10 5:00 ` Anup Patel
2025-06-10 5:00 ` Anup Patel
2025-05-25 8:46 ` [PATCH v4 09/23] dt-bindings: clock: Add RPMI clock service controller bindings Anup Patel
2025-05-25 8:46 ` Anup Patel
2025-05-30 16:41 ` Conor Dooley
2025-05-30 16:41 ` Conor Dooley
2025-06-10 5:20 ` Anup Patel
2025-06-10 5:20 ` Anup Patel
2025-05-25 8:46 ` [PATCH v4 10/23] clk: Add clock driver for the RISC-V RPMI clock service group Anup Patel
2025-05-25 8:46 ` Anup Patel
2025-05-25 8:46 ` [PATCH v4 11/23] dt-bindings: Add RPMI system MSI message proxy bindings Anup Patel
2025-05-25 8:46 ` Anup Patel
2025-06-06 22:59 ` Atish Patra
2025-06-06 22:59 ` Atish Patra
2025-06-10 6:09 ` Anup Patel
2025-06-10 6:09 ` Anup Patel
2025-05-25 8:46 ` [PATCH v4 12/23] dt-bindings: Add RPMI system MSI interrupt controller bindings Anup Patel
2025-05-25 8:46 ` Anup Patel
2025-06-06 23:03 ` Atish Patra
2025-06-06 23:03 ` Atish Patra
2025-06-10 6:22 ` Anup Patel
2025-06-10 6:22 ` Anup Patel
2025-05-25 8:47 ` [PATCH v4 13/23] irqchip: Add driver for the RPMI system MSI service group Anup Patel
2025-05-25 8:47 ` Anup Patel
2025-05-27 11:33 ` Andy Shevchenko
2025-05-27 11:33 ` Andy Shevchenko
2025-06-10 11:03 ` Anup Patel
2025-06-10 11:03 ` Anup Patel
2025-06-11 8:22 ` Andy Shevchenko
2025-06-11 8:22 ` Andy Shevchenko
2025-05-25 8:47 ` [PATCH v4 14/23] ACPI: property: Refactor acpi_fwnode_get_reference_args() Anup Patel
2025-05-25 8:47 ` Anup Patel
2025-05-25 8:47 ` [PATCH v4 15/23] ACPI: property: Add support for cells property Anup Patel
2025-05-25 8:47 ` Anup Patel
2025-05-25 8:47 ` [PATCH v4 16/23] ACPI: scan: Update honor list for RPMI System MSI Anup Patel
2025-05-25 8:47 ` Anup Patel
2025-05-25 8:47 ` [PATCH v4 17/23] ACPI: RISC-V: Create interrupt controller list in sorted order Anup Patel
2025-05-25 8:47 ` Anup Patel
2025-05-28 11:05 ` Andy Shevchenko
2025-05-28 11:05 ` Andy Shevchenko
2025-06-10 4:42 ` Sunil V L
2025-06-10 4:42 ` Sunil V L
2025-06-11 8:21 ` Andy Shevchenko
2025-06-11 8:21 ` Andy Shevchenko
2025-05-25 8:47 ` [PATCH v4 18/23] ACPI: RISC-V: Add support to update gsi range Anup Patel
2025-05-25 8:47 ` Anup Patel
2025-05-25 8:47 ` [PATCH v4 19/23] ACPI: RISC-V: Add RPMI System MSI to GSI mapping Anup Patel
2025-05-25 8:47 ` Anup Patel
2025-05-25 8:47 ` [PATCH v4 20/23] mailbox/riscv-sbi-mpxy: Add ACPI support Anup Patel
2025-05-25 8:47 ` Anup Patel
2025-05-25 8:47 ` [PATCH v4 21/23] irqchip/riscv-rpmi-sysmsi: " Anup Patel
2025-05-25 8:47 ` Anup Patel
2025-05-25 8:47 ` [PATCH v4 22/23] RISC-V: Enable GPIO keyboard and event device in RV64 defconfig Anup Patel
2025-05-25 8:47 ` Anup Patel
2025-05-25 8:47 ` [PATCH v4 23/23] MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers Anup Patel
2025-05-25 8:47 ` Anup Patel
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