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Tue, 10 Jun 2025 20:59:56 -0700 (PDT) Received: from geday ([2804:7f2:800b:5f6a::dead:c001]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-53113c0ee7fsm2411261e0c.41.2025.06.10.20.59.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 20:59:55 -0700 (PDT) Date: Wed, 11 Jun 2025 00:59:48 -0300 From: Geraldo Nascimento To: Bjorn Helgaas Cc: linux-rockchip@lists.infradead.org, Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 1/4] PCI: pcie-rockchip: add bits for Target Link Speed in LCS_2 Message-ID: References: <20250610200744.GA820589@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250610_205957_649994_3B65FC92 X-CRM114-Status: GOOD ( 12.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jun 11, 2025 at 12:46:10AM -0300, Geraldo Nascimento wrote: > Hi again Bjorn, > > Your message reminded me of something that may be important. > > During my debugging I had the mild impression L0s capability is not > being cleared from Link Capabilities Register in the presence of > "aspm-no-l0s" DT property. > > I can't confirm it right now but I might revisit this later on. From > what I've seen it can only be cleared from inside the port init > in pcie-rockchip.c and does nothing in present form. > > Not a clear, confirmable report but something to watch out for... Not correct. ASPM bit for L0s is being properly cleared according to my printk's. Should have checked before creating noise. Sorry. Geraldo Nascimento > > Regards, > Geraldo Nascimento From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E83E9C677C4 for ; Wed, 11 Jun 2025 04:02:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=x14RnHn4Wuh5jJi/P40pmsQS55rzKlysSF9XXKSG3sg=; b=0BKz2TnWvLYCjY FP/fYTK+RvO0rt2nV677JnaqTQIpwLgOycMOxw2plrJzG4qF8yeGelR1pbPDvPZccak8EQCl8AMiN 6uhyvx+we0eqUvvmub5l0I6IJYO2zTqFA9x7PUjEhlQgG9FNEQf9MjqB9QWUuJNyZRJg8OS31kms2 ecP1vo2WeHD+fTI03Ej6AFsN2AlaA/1FPP1OoJYtH501F/aZs0p800wgw/LVd2OvYV2iQMKhkK4Jt o9T6ASPyZuvo97neTOXyLOB4kJdWmrqIn56VCR3nOrsoN+ydkmZ5K+ClVw7E+5z8gNnGsqfuHCJhT 9rLYzq7wV8HS5n+w3u4Q==; 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Tue, 10 Jun 2025 20:59:56 -0700 (PDT) Received: from geday ([2804:7f2:800b:5f6a::dead:c001]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-53113c0ee7fsm2411261e0c.41.2025.06.10.20.59.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jun 2025 20:59:55 -0700 (PDT) Date: Wed, 11 Jun 2025 00:59:48 -0300 From: Geraldo Nascimento To: Bjorn Helgaas Cc: linux-rockchip@lists.infradead.org, Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 1/4] PCI: pcie-rockchip: add bits for Target Link Speed in LCS_2 Message-ID: References: <20250610200744.GA820589@bhelgaas> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250610_205957_649994_3B65FC92 X-CRM114-Status: GOOD ( 12.03 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Wed, Jun 11, 2025 at 12:46:10AM -0300, Geraldo Nascimento wrote: > Hi again Bjorn, > > Your message reminded me of something that may be important. > > During my debugging I had the mild impression L0s capability is not > being cleared from Link Capabilities Register in the presence of > "aspm-no-l0s" DT property. > > I can't confirm it right now but I might revisit this later on. From > what I've seen it can only be cleared from inside the port init > in pcie-rockchip.c and does nothing in present form. > > Not a clear, confirmable report but something to watch out for... Not correct. ASPM bit for L0s is being properly cleared according to my printk's. Should have checked before creating noise. Sorry. Geraldo Nascimento > > Regards, > Geraldo Nascimento -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 69169C677C4 for ; Wed, 11 Jun 2025 04:02:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 10 Jun 2025 20:59:55 -0700 (PDT) Date: Wed, 11 Jun 2025 00:59:48 -0300 From: Geraldo Nascimento To: Bjorn Helgaas Cc: linux-rockchip@lists.infradead.org, Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 1/4] PCI: pcie-rockchip: add bits for Target Link Speed in LCS_2 Message-ID: References: <20250610200744.GA820589@bhelgaas> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250610_205957_649994_3B65FC92 X-CRM114-Status: GOOD ( 12.03 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org On Wed, Jun 11, 2025 at 12:46:10AM -0300, Geraldo Nascimento wrote: > Hi again Bjorn, > > Your message reminded me of something that may be important. > > During my debugging I had the mild impression L0s capability is not > being cleared from Link Capabilities Register in the presence of > "aspm-no-l0s" DT property. > > I can't confirm it right now but I might revisit this later on. From > what I've seen it can only be cleared from inside the port init > in pcie-rockchip.c and does nothing in present form. > > Not a clear, confirmable report but something to watch out for... Not correct. ASPM bit for L0s is being properly cleared according to my printk's. Should have checked before creating noise. Sorry. Geraldo Nascimento > > Regards, > Geraldo Nascimento _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip