From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DBB32EA726; Wed, 18 Jun 2025 16:12:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750263132; cv=none; b=ryvX+FHq5f6+WaFnojQA0UnefmFBKlovMzdzuPn9rxv5j7OYiehVBkDQBzPYa5rvsowJNrh0Q/5vNexKgXsPO3pl+g+7CEFj6/dFYzSIBX1Dyzb+XDRLw/csSsKzqpw3YrhO3Ik7V+wE3AHsKNGBtak1OK8ApMif1Yzn9T2HMd0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750263132; c=relaxed/simple; bh=i8mkfLjVV8yEGW3Qn3c+2xvhyBSRGg3kpOmHpVtfP2E=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=UDOljVV1Q6UrtuwzTIifFpXYp4olU/VvSAzzuvmbCvPTSfbyb0KtyUudRvHUjY3c1lVD+B6a8Aetv5Dxs+Gzb9V0iJNnuJKl2wDYVEweHc2R9yzky7oheZmC9NMaItzE8P+KGwtcggFqJ2L32ueplBI5u/0q83soIDWv2/i8vU8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id B8885C4CEE7; Wed, 18 Jun 2025 16:12:04 +0000 (UTC) Date: Wed, 18 Jun 2025 17:12:02 +0100 From: Catalin Marinas To: ankita@nvidia.com Cc: jgg@nvidia.com, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, will@kernel.org, ryan.roberts@arm.com, shahuang@redhat.com, lpieralisi@kernel.org, david@redhat.com, ddutile@redhat.com, seanjc@google.com, aniketa@nvidia.com, cjia@nvidia.com, kwankhede@nvidia.com, kjaju@nvidia.com, targupta@nvidia.com, vsethi@nvidia.com, acurrid@nvidia.com, apopple@nvidia.com, jhubbard@nvidia.com, danw@nvidia.com, zhiw@nvidia.com, mochs@nvidia.com, udhoke@nvidia.com, dnigam@nvidia.com, alex.williamson@redhat.com, sebastianene@google.com, coltonlewis@google.com, kevin.tian@intel.com, yi.l.liu@intel.com, ardb@kernel.org, akpm@linux-foundation.org, gshan@redhat.com, linux-mm@kvack.org, tabba@google.com, qperret@google.com, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, maobibo@loongson.cn Subject: Re: [PATCH v7 3/5] KVM: arm64: New function to determine hardware cache management support Message-ID: References: <20250618065541.50049-1-ankita@nvidia.com> <20250618065541.50049-4-ankita@nvidia.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250618065541.50049-4-ankita@nvidia.com> On Wed, Jun 18, 2025 at 06:55:39AM +0000, ankita@nvidia.com wrote: > From: Ankit Agrawal > > VM_PFNMAP VMA's are allowed to contain PTE's which point to physical > addresses that does not have a struct page and may not be in the kernel > direct map. > > However ARM64 KVM relies on a simple conversion from physaddr to a > kernel virtual address when it does cache maintenance as the CMO > instructions work on virtual addresses. This simple approach does not > work for physical addresses from VM_PFNMAP since those addresses may > not have a kernel virtual address, or it may be difficult to find it. > > Fortunately if the ARM64 CPU has two features, S2FWB and CACHE DIC, > then KVM no longer needs to do cache flushing and NOP's all the > CMOs. This has the effect of no longer requiring a KVA for addresses > mapped into the S2. > > Add a new function, kvm_arch_supports_cacheable_pfnmap(), to report > this capability. From a core prespective it means the arch can accept > a cachable VM_PFNMAP as a memslot. From an ARM64 perspective it means > that no KVA is required. > > CC: Jason Gunthorpe > CC: David Hildenbrand > CC: Donald Dutile > Signed-off-by: Ankit Agrawal Reviewed-by: Catalin Marinas