From: Shawn Guo <shawnguo2@yeah.net>
To: James Clark <james.clark@linaro.org>
Cc: Vladimir Oltean <olteanv@gmail.com>,
Mark Brown <broonie@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Matti Vaittinen <mazziesaccount@gmail.com>,
Conor Dooley <conor+dt@kernel.org>, Frank Li <Frank.Li@nxp.com>,
Chester Lin <chester62515@gmail.com>,
Matthias Brugger <mbrugger@suse.com>,
Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>,
NXP S32 Linux Team <s32@nxp.com>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
Chao Fu <B44548@freescale.com>, Xiubo Li <Li.Xiubo@freescale.com>,
Lukasz Majewski <lukma@denx.de>,
linux-spi@vger.kernel.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Vladimir Oltean <vladimir.oltean@nxp.com>,
Dan Carpenter <dan.carpenter@linaro.org>,
Larisa Grigore <larisa.grigore@nxp.com>,
"Radu Pirea (NXP OSS)" <radu-nicolae.pirea@oss.nxp.com>
Subject: Re: [PATCH v2 14/14] arm64: dts: Add DSPI entries for S32G platforms
Date: Thu, 19 Jun 2025 15:38:46 +0800 [thread overview]
Message-ID: <aFO+htx92aa90SL0@dragon> (raw)
In-Reply-To: <20250522-james-nxp-spi-v2-14-bea884630cfb@linaro.org>
On Thu, May 22, 2025 at 03:51:43PM +0100, James Clark wrote:
> From: Larisa Grigore <larisa.grigore@nxp.com>
>
> S32G3 and S32G2 have the same 6 SPI devices, add the DT entries. Devices
> are all the same except spi0 has 8 chip selects instead of 5. Clock
> settings for the chip rely on ATF Firmware [1].
>
> [1]: https://github.com/nxp-auto-linux/arm-trusted-firmware
> Co-developed-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com>
> Signed-off-by: Radu Pirea (NXP OSS) <radu-nicolae.pirea@oss.nxp.com>
> Signed-off-by: Larisa Grigore <Larisa.Grigore@nxp.com>
> Signed-off-by: James Clark <james.clark@linaro.org>
> ---
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 78 +++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 78 +++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi | 83 +++++++++++++++++++++++++
> arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi | 83 +++++++++++++++++++++++++
> 4 files changed, 322 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index ea1456d361a3..68848575bf81 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -376,6 +376,45 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + spi0: spi@401d4000 {
> + compatible = "nxp,s32g2-dspi";
> + reg = <0x401d4000 0x1000>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 26>;
> + clock-names = "dspi";
> + spi-num-chipselects = <8>;
> + bus-num = <0>;
> + dmas = <&edma0 0 7>, <&edma0 0 8>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + spi1: spi@401d8000 {
> + compatible = "nxp,s32g2-dspi";
> + reg = <0x401d8000 0x1000>;
> + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 26>;
> + clock-names = "dspi";
> + spi-num-chipselects = <5>;
> + bus-num = <1>;
> + dmas = <&edma0 0 10>, <&edma0 0 11>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + spi2: spi@401dc000 {
> + compatible = "nxp,s32g2-dspi";
> + reg = <0x401dc000 0x1000>;
> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 26>;
> + clock-names = "dspi";
> + spi-num-chipselects = <5>;
> + bus-num = <2>;
> + dmas = <&edma0 0 13>, <&edma0 0 14>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> i2c0: i2c@401e4000 {
> compatible = "nxp,s32g2-i2c";
> reg = <0x401e4000 0x1000>;
> @@ -460,6 +499,45 @@ uart2: serial@402bc000 {
> status = "disabled";
> };
>
> + spi3: spi@402c8000 {
> + compatible = "nxp,s32g2-dspi";
> + reg = <0x402c8000 0x1000>;
> + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 26>;
> + clock-names = "dspi";
> + spi-num-chipselects = <5>;
> + bus-num = <3>;
> + dmas = <&edma0 1 7>, <&edma0 1 8>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + spi4: spi@402cc000 {
> + compatible = "nxp,s32g2-dspi";
> + reg = <0x402cc000 0x1000>;
> + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 26>;
> + clock-names = "dspi";
> + spi-num-chipselects = <5>;
> + bus-num = <4>;
> + dmas = <&edma0 1 10>, <&edma0 1 11>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + spi5: spi@402d0000 {
> + compatible = "nxp,s32g2-dspi";
> + reg = <0x402d0000 0x1000>;
> + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 26>;
> + clock-names = "dspi";
> + spi-num-chipselects = <5>;
> + bus-num = <5>;
> + dmas = <&edma0 1 13>, <&edma0 1 14>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> i2c3: i2c@402d8000 {
> compatible = "nxp,s32g2-i2c";
> reg = <0x402d8000 0x1000>;
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 991dbfbfa203..4f883b1a50ad 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -435,6 +435,45 @@ uart1: serial@401cc000 {
> status = "disabled";
> };
>
> + spi0: spi@401d4000 {
> + compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
> + reg = <0x401d4000 0x1000>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 26>;
> + clock-names = "dspi";
> + spi-num-chipselects = <8>;
> + bus-num = <0>;
> + dmas = <&edma0 0 7>, <&edma0 0 8>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + spi1: spi@401d8000 {
> + compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
> + reg = <0x401d8000 0x1000>;
> + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 26>;
> + clock-names = "dspi";
> + spi-num-chipselects = <5>;
> + bus-num = <1>;
> + dmas = <&edma0 0 10>, <&edma0 0 11>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + spi2: spi@401dc000 {
> + compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
> + reg = <0x401dc000 0x1000>;
> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 26>;
> + clock-names = "dspi";
> + spi-num-chipselects = <5>;
> + bus-num = <2>;
> + dmas = <&edma0 0 13>, <&edma0 0 14>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> i2c0: i2c@401e4000 {
> compatible = "nxp,s32g3-i2c",
> "nxp,s32g2-i2c";
> @@ -524,6 +563,45 @@ uart2: serial@402bc000 {
> status = "disabled";
> };
>
> + spi3: spi@402c8000 {
> + compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
> + reg = <0x402c8000 0x1000>;
> + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 26>;
> + clock-names = "dspi";
> + spi-num-chipselects = <5>;
> + bus-num = <3>;
> + dmas = <&edma0 1 7>, <&edma0 1 8>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + spi4: spi@402cc000 {
> + compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
> + reg = <0x402cc000 0x1000>;
> + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 26>;
> + clock-names = "dspi";
> + spi-num-chipselects = <5>;
> + bus-num = <4>;
> + dmas = <&edma0 1 10>, <&edma0 1 11>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + spi5: spi@402d0000 {
> + compatible = "nxp,s32g3-dspi", "nxp,s32g2-dspi";
> + reg = <0x402d0000 0x1000>;
> + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks 26>;
> + clock-names = "dspi";
> + spi-num-chipselects = <5>;
> + bus-num = <5>;
> + dmas = <&edma0 1 13>, <&edma0 1 14>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> i2c3: i2c@402d8000 {
> compatible = "nxp,s32g3-i2c",
> "nxp,s32g2-i2c";
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> index d26af0fb8be7..d8bf734aa267 100644
> --- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> @@ -173,6 +173,77 @@ i2c4-gpio-grp1 {
> pinmux = <0x2d40>, <0x2d30>;
> };
> };
> +
> + dspi1_pins: dspi1-pins {
> + dspi1-grp0 {
> + pinmux = <0x72>;
> + output-enable;
> + input-enable;
> + slew-rate = <150>;
> + bias-pull-up;
> + };
> +
> + dspi1-grp1 {
> + pinmux = <0x62>;
> + output-enable;
> + slew-rate = <150>;
> + };
> +
> + dspi1-grp2 {
> + pinmux = <0x83>;
> + output-enable;
> + input-enable;
> + slew-rate = <150>;
> + };
> +
> + dspi1-grp3 {
> + pinmux = <0x5F0>;
> + input-enable;
> + slew-rate = <150>;
> + bias-pull-up;
> + };
> +
> + dspi1-grp4 {
> + pinmux = <0x3D92>,
> + <0x3DA2>,
> + <0x3DB2>;
> + };
> + };
> +
> + dspi5_pins: dspi5-pins {
> + dspi5-grp0 {
> + pinmux = <0x93>;
> + output-enable;
> + input-enable;
> + slew-rate = <150>;
> + };
> +
> + dspi5-grp1 {
> + pinmux = <0xA0>;
> + input-enable;
> + slew-rate = <150>;
> + bias-pull-up;
> + };
> +
> + dspi5-grp2 {
> + pinmux = <0x3ED2>,
> + <0x3EE2>,
> + <0x3EF2>;
> + };
> +
> + dspi5-grp3 {
> + pinmux = <0xB3>;
> + output-enable;
> + slew-rate = <150>;
> + };
Missing a newline.
I fixed it up and applied the patch.
Shawn
> + dspi5-grp4 {
> + pinmux = <0xC3>;
> + output-enable;
> + input-enable;
> + slew-rate = <150>;
> + bias-pull-up;
> + };
> + };
> };
>
> &can0 {
> @@ -220,3 +291,15 @@ &i2c4 {
> pinctrl-1 = <&i2c4_gpio_pins>;
> status = "okay";
> };
> +
> +&spi1 {
> + pinctrl-0 = <&dspi1_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&spi5 {
> + pinctrl-0 = <&dspi5_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> index ba53ec622f0b..b0a21e4468da 100644
> --- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> @@ -127,6 +127,77 @@ i2c4-gpio-grp1 {
> pinmux = <0x2d40>, <0x2d30>;
> };
> };
> +
> + dspi1_pins: dspi1-pins {
> + dspi1-grp0 {
> + pinmux = <0x72>;
> + output-enable;
> + input-enable;
> + slew-rate = <150>;
> + bias-pull-up;
> + };
> +
> + dspi1-grp1 {
> + pinmux = <0x62>;
> + output-enable;
> + slew-rate = <150>;
> + };
> +
> + dspi1-grp2 {
> + pinmux = <0x83>;
> + output-enable;
> + input-enable;
> + slew-rate = <150>;
> + };
> +
> + dspi1-grp3 {
> + pinmux = <0x5F0>;
> + input-enable;
> + slew-rate = <150>;
> + bias-pull-up;
> + };
> +
> + dspi1-grp4 {
> + pinmux = <0x3D92>,
> + <0x3DA2>,
> + <0x3DB2>;
> + };
> + };
> +
> + dspi5_pins: dspi5-pins {
> + dspi5-grp0 {
> + pinmux = <0x93>;
> + output-enable;
> + input-enable;
> + slew-rate = <150>;
> + };
> +
> + dspi5-grp1 {
> + pinmux = <0xA0>;
> + input-enable;
> + slew-rate = <150>;
> + bias-pull-up;
> + };
> +
> + dspi5-grp2 {
> + pinmux = <0x3ED2>,
> + <0x3EE2>,
> + <0x3EF2>;
> + };
> +
> + dspi5-grp3 {
> + pinmux = <0xB3>;
> + output-enable;
> + slew-rate = <150>;
> + };
> + dspi5-grp4 {
> + pinmux = <0xC3>;
> + output-enable;
> + input-enable;
> + slew-rate = <150>;
> + bias-pull-up;
> + };
> + };
> };
>
> &can0 {
> @@ -155,6 +226,18 @@ pcal6524: gpio-expander@22 {
> };
> };
>
> +&spi1 {
> + pinctrl-0 = <&dspi1_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&spi5 {
> + pinctrl-0 = <&dspi5_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> &i2c2 {
> pinctrl-names = "default", "gpio";
> pinctrl-0 = <&i2c2_pins>;
>
> --
> 2.34.1
>
next prev parent reply other threads:[~2025-06-19 7:41 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-22 14:51 [PATCH v2 00/14] spi: spi-fsl-dspi: DSPI support for NXP S32G platforms James Clark
2025-05-22 14:51 ` [PATCH v2 01/14] spi: spi-fsl-dspi: restrict register range for regmap access James Clark
2025-05-22 14:51 ` [PATCH v2 02/14] spi: spi-fsl-dspi: Halt the module after a new message transfer James Clark
2025-05-22 14:51 ` [PATCH v2 03/14] spi: spi-fsl-dspi: Reset SR flags before sending a new message James Clark
2025-05-22 14:51 ` [PATCH v2 04/14] spi: spi-fsl-dspi: Re-use one volatile regmap for both device types James Clark
2025-05-22 14:51 ` [PATCH v2 05/14] spi: spi-fsl-dspi: Define regmaps per device James Clark
2025-05-22 14:51 ` [PATCH v2 06/14] spi: spi-fsl-dspi: Add config and regmaps for S32G platforms James Clark
2025-05-22 14:51 ` [PATCH v2 07/14] spi: spi-fsl-dspi: Use spi_alloc_target for target James Clark
2025-05-22 14:51 ` [PATCH v2 08/14] spi: spi-fsl-dspi: Avoid setup_accel logic for DMA transfers James Clark
2025-05-22 14:51 ` [PATCH v2 09/14] spi: spi-fsl-dspi: Use DMA for S32G controller in target mode James Clark
2025-05-22 14:51 ` [PATCH v2 10/14] spi: spi-fsl-dspi: Reinitialize DSPI regs after resuming for S32G James Clark
2025-05-22 14:51 ` [PATCH v2 11/14] spi: spi-fsl-dspi: Enable modified transfer protocol on S32G James Clark
2025-05-22 14:51 ` [PATCH v2 12/14] dt-bindings: spi: dspi: Add S32G support James Clark
2025-05-22 14:51 ` [PATCH v2 13/14] spi: spi-fsl-dspi: Enable support for S32G platforms James Clark
2025-05-22 14:51 ` [PATCH v2 14/14] arm64: dts: Add DSPI entries " James Clark
2025-06-19 7:38 ` Shawn Guo [this message]
2025-05-22 17:17 ` (subset) [PATCH v2 00/14] spi: spi-fsl-dspi: DSPI support for NXP " Mark Brown
2025-06-09 19:33 ` Mark Brown
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aFO+htx92aa90SL0@dragon \
--to=shawnguo2@yeah.net \
--cc=B44548@freescale.com \
--cc=Frank.Li@nxp.com \
--cc=Li.Xiubo@freescale.com \
--cc=broonie@kernel.org \
--cc=chester62515@gmail.com \
--cc=conor+dt@kernel.org \
--cc=dan.carpenter@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=festevam@gmail.com \
--cc=ghennadi.procopciuc@oss.nxp.com \
--cc=imx@lists.linux.dev \
--cc=james.clark@linaro.org \
--cc=kernel@pengutronix.de \
--cc=krzk+dt@kernel.org \
--cc=larisa.grigore@nxp.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=lukma@denx.de \
--cc=mazziesaccount@gmail.com \
--cc=mbrugger@suse.com \
--cc=olteanv@gmail.com \
--cc=radu-nicolae.pirea@oss.nxp.com \
--cc=robh@kernel.org \
--cc=s.hauer@pengutronix.de \
--cc=s32@nxp.com \
--cc=shawnguo@kernel.org \
--cc=vladimir.oltean@nxp.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.