Re: [PATCH v3 4/4] dma: dw-axi-dmac: Add support for dma-bit-mask property

[Vinod Koul <vkoul@kernel.org>]

On 16-06-25, 22:40, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Please change subsystem tag to dmanegine: xxx

> 
> Intel Agilex5 address bus only supports up to 40 bits. Add dma-bit-mask
> property support where configure dma-bit-mask based on dma-bit-mask
> property or fallback to default value if property is not present.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> Reviewed-by: Matthew Gerlach <matthew.gerlach@altrera.com>
> 
> v3:
> -update to read from updated property name.
> 
> v2:
> -Fix build errors and warning
> ---
>  drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index b23536645ff7..e56ff7aadafd 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -265,13 +265,23 @@ static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan)
>  static void axi_dma_hw_init(struct axi_dma_chip *chip)
>  {
>  	int ret;
> -	u32 i;
> +	u32 i, tmp;
>  
>  	for (i = 0; i < chip->dw->hdata->nr_channels; i++) {
>  		axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
>  		axi_chan_disable(&chip->dw->chan[i]);
>  	}
> -	ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
> +
> +	ret = device_property_read_u32(chip->dev, "snps,dma-addressable-bits", &tmp);
> +	if (ret)
> +		ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
> +	else {
> +		if (tmp == 0 || tmp < 32 || tmp > 64)
> +			dev_err(chip->dev, "Invalid dma bit mask\n");
> +
> +		ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(tmp));

why not check the mask value and set that only once irrespective of
mask, it can tmp or 64!

-- 
~Vinod