Re: [PATCH v3 07/10] clk: socfpga: add agilex5 clock support

[Sascha Hauer <s.hauer@pengutronix.de>]

On Mon, Jun 23, 2025 at 03:57:52PM +0200, Steffen Trumtrar wrote:
> +
> +static int agilex5_clkmgr_probe(struct device *dev)
> +{
> +	struct device_node *np = dev->of_node;
> +	struct stratix10_clock_data *clk_data;
> +	struct resource *res;
> +	int i, num_clks;
> +
> +	res = dev_get_resource(dev, IORESOURCE_MEM, 0);
> +	if (IS_ERR(res))
> +		return PTR_ERR(res);

dev_get_resource() should only be used when you know it is used
somewhere else as well. Otherwise please use dev_request_mem_resource().
That way you will recognize conflicts and as an additional bonus the
resource will show up in iomem ooutput.

> +static int __init agilex5_clk_init(void)
> +{
> +	return platform_driver_register(&agilex5_clkmgr_driver);
> +}
> +core_initcall(agilex5_clk_init);

You could use core_platform_driver here.


> +static unsigned long clk_peri_c_clk_recalc_rate(struct clk_hw *hwclk,
> +					     unsigned long parent_rate)
> +{
> +	struct socfpga_periph_clk *socfpgaclk = to_periph_clk(hwclk);
> +	unsigned long div = 1;
> +	u32 val;
> +
> +	val = readl(socfpgaclk->reg);
> +	val &= GENMASK(SWCTRLBTCLKSEN_SHIFT - 1, 0);
> +	parent_rate /= val;
> +
> +	return parent_rate / div;

div is always 1.

> +}
> +
> +struct clk_hw *agilex5_register_pll(const struct stratix10_pll_clock *clks,
> +				void __iomem *reg)
> +{
> +	struct clk_hw *hw_clk;
> +	struct socfpga_pll *pll_clk;
> +	struct clk_init_data init;
> +	const char *name = clks->name;
> +	int ret;
> +
> +	pll_clk = xzalloc(sizeof(*pll_clk));
> +	if (!pll_clk)
> +		return ERR_PTR(-ENOMEM);

xzalloc never fails.

You kept the original kzalloc in some places and replaced with xzalloc
elsewhere. Could you use xzalloc consistently?

Sascha

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