Re: [PATCH 3/3] drm/i915/power: convert {SKL, ICL}_PW_CTL_IDX_TO_PG() macros to a function

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Wed, Jun 25, 2025 at 03:39:38PM +0300, Jani Nikula wrote:
> Add pw_ctl_idx_to_pg() helper function to deduplicate the open-coded
> usage of the {SKL,ICL}_PW_CTL_IDX_TO_PG() macros.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  .../i915/display/intel_display_power_well.c   | 24 +++++++++----------
>  1 file changed, 11 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 9d60dfc4939d..4a876fa815bd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -36,16 +36,15 @@
>  
>  /*
>   * PG0 is HW controlled, so doesn't have a corresponding power well control knob
> - * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
> - */
> -#define  SKL_PW_CTL_IDX_TO_PG(pw_idx)		\
> -	((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
> -/*
> - * PG0 is HW controlled, so doesn't have a corresponding power well control knob
> - * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
> + *
> + * {ICL,SKL}_DISP_PW1_IDX..{ICL,SKL}_DISP_PW4_IDX -> PG1..PG4
>   */
> -#define  ICL_PW_CTL_IDX_TO_PG(pw_idx)		\
> -	((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
> +static enum skl_power_gate pw_idx_to_pg(struct intel_display *display, int pw_idx)
> +{
> +	int pw1_idx = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_PW_1 : SKL_PW_CTL_IDX_PW_1;
> +
> +	return pw_idx - pw1_idx + SKL_PG1;

\o/ I hate macros! :)

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> +}
>  
>  struct i915_power_well_regs {
>  	i915_reg_t bios;
> @@ -363,8 +362,7 @@ static void hsw_power_well_enable(struct intel_display *display,
>  	if (power_well->desc->has_fuses) {
>  		enum skl_power_gate pg;
>  
> -		pg = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
> -						 SKL_PW_CTL_IDX_TO_PG(pw_idx);
> +		pg = pw_idx_to_pg(display, pw_idx);
>  
>  		/* Wa_16013190616:adlp */
>  		if (display->platform.alderlake_p && pg == SKL_PG1)
> @@ -388,8 +386,8 @@ static void hsw_power_well_enable(struct intel_display *display,
>  	if (power_well->desc->has_fuses) {
>  		enum skl_power_gate pg;
>  
> -		pg = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
> -						 SKL_PW_CTL_IDX_TO_PG(pw_idx);
> +		pg = pw_idx_to_pg(display, pw_idx);
> +
>  		gen9_wait_for_power_well_fuses(display, pg);
>  	}
>  
> -- 
> 2.39.5
>