From: Lukas Wunner <lukas@wunner.de>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: Laurent Bigonville <bigon@bigon.be>,
Mario Limonciello <mario.limonciello@amd.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Mika Westerberg <westeri@kernel.org>,
linux-pci@vger.kernel.org
Subject: Re: [PATCH] PCI/ACPI: Fix runtime PM ref imbalance on hot-plug capable ports
Date: Thu, 26 Jun 2025 07:20:26 +0200 [thread overview]
Message-ID: <aFzYmpxOlRdRFTfl@wunner.de> (raw)
In-Reply-To: <20250625193231.GA1582741@bhelgaas>
On Wed, Jun 25, 2025 at 02:32:31PM -0500, Bjorn Helgaas wrote:
> On Wed, Jun 25, 2025 at 09:37:38AM +0200, Lukas Wunner wrote:
> > On Tue, Jun 24, 2025 at 09:24:07AM -0500, Bjorn Helgaas wrote:
> > > It doesn't look like anything in pci_bridge_d3_possible() should
> > > change over the life of the device, although acpi_pci_bridge_d3() is
> > > non-trivial.
> > >
> > > Should we consider calling pci_bridge_d3_possible() only once and
> > > caching the result? We already call it in pci_pm_init() and save the
> > > result in dev->bridge_d3. That member can be changed by
> > > pci_bridge_d3_update(), but we could add another copy that we never
> > > update after pci_pm_init().
> >
> > If we did that, I think we'd still want to have a WARN_ON() like this in
> > pcie_portdrv_remove():
> >
> > + WARN_ON(dev->bridge_d3_orig != pci_bridge_d3_possible(dev));
> > +
> > + if (dev->bridge_d3_orig) {
> > - if (pci_bridge_d3_possible(dev)) {
> >
> > Because without the WARN_ON(), such bugs would fly under the radar.
> >
> > However currently we get the WARN_ON() for free because of the runtime PM
> > refcount underflow.
> >
> > So caching the original return value of pci_bridge_d3_possible(dev)
> > wouldn't be a net positive.
[...]
> But I feel like I'm missing your point about bugs flying under the
> radar. Having portdrv keep track of whether it did runtime PM setup
> (i.e., the pci_bridge_d3_possible() state at .probe()-time) is
> functionally the same as having struct pci_dev keep track of it, so
> the bugs you're referring to could still fly under the radar.
So the return value of pci_bridge_d3_possible() should never change
over the lifetime of a device. We're also invoking that function
from pci_bridge_d3_update() and the logic would no longer work
if the return value changed.
My point is that we're currently verifying that the return value
hasn't changed by regenerating it in pcie_portdrv_remove().
If it *has* changed, the runtime PM ref imbalance occurs and we get
a warning message.
If we instead cached the value in pcie_portdrv_probe(), we wouldn't
have found this bug.
Does that make sense?
Thanks,
Lukas
next prev parent reply other threads:[~2025-06-26 5:20 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-23 17:08 [PATCH] PCI/ACPI: Fix runtime PM ref imbalance on hot-plug capable ports Lukas Wunner
2025-06-23 17:15 ` Rafael J. Wysocki
2025-06-23 21:59 ` Mario Limonciello
2025-06-24 4:42 ` Mika Westerberg
2025-06-24 14:24 ` Bjorn Helgaas
2025-06-25 7:37 ` Lukas Wunner
2025-06-25 8:56 ` Rafael J. Wysocki
2025-06-25 19:32 ` Bjorn Helgaas
2025-06-26 5:20 ` Lukas Wunner [this message]
2025-06-26 5:30 ` Lukas Wunner
2025-06-26 9:47 ` Rafael J. Wysocki
2025-06-26 11:59 ` Ilpo Järvinen
2025-06-27 2:56 ` Bjorn Helgaas
2025-07-13 15:20 ` Lukas Wunner
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