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Thu, 10 Jul 2025 10:25:55 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Thu, 10 Jul 2025 10:25:54 -0700 Received: from Asurada-Nvidia (10.127.8.14) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14 via Frontend Transport; Thu, 10 Jul 2025 10:25:54 -0700 Date: Thu, 10 Jul 2025 10:25:52 -0700 From: Nicolin Chen To: Donald Dutile CC: Shameerali Kolothum Thodi , Zhenzhong Duan , "qemu-devel@nongnu.org" , "alex.williamson@redhat.com" , "clg@redhat.com" , "eric.auger@redhat.com" , "mst@redhat.com" , "jasowang@redhat.com" , "peterx@redhat.com" , "jgg@nvidia.com" , "joao.m.martins@oracle.com" , "clement.mathieu--drif@eviden.com" , "kevin.tian@intel.com" , "yi.l.liu@intel.com" , "chao.p.peng@intel.com" Subject: Re: [PATCH v3 02/20] hw/pci: Introduce pci_device_get_viommu_cap() Message-ID: References: <20250708110601.633308-1-zhenzhong.duan@intel.com> <20250708110601.633308-3-zhenzhong.duan@intel.com> <01584206-e2c0-4881-aaf5-d6c552a30873@redhat.com> <5542e55f-5cd9-40f8-bb45-fe6d851140b1@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 17:26:08.6556 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 66f119c8-b16b-4914-1af8-08ddbfd6dbd4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB77.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6590 Received-SPF: permerror client-ip=2a01:111:f403:2415::62f; envelope-from=nicolinc@nvidia.com; helo=NAM11-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Jul 10, 2025 at 01:07:11PM -0400, Donald Dutile wrote: > > > > If not, maybe go a bit further like "VIOMMU_CAP_HW_NESTED_S1"? > > > > > > I am not sure the _S1 part makes much sense in ARM case. It doesn't matter > > > whether the Guest SMMUv3 is configured in s1/s2 or nested for this CAP. > > > With the new SMMUv3 dev support, the user can pretty much specify, > > > > > > -device arm-smmuv3,primary-bus=pcie.0,id=smmuv3.1,accel=on,stage={stage1|stage2|nested} > > > > > > And I think it will work with a host SMMUv3 nested configuration in all the > > > above cases. Unless I am missing something and we need to restrict its > > > use with stage=stage1 only. > > > > > > Thanks, > > > Shameer > > > > Shameer, > I didn't think of these config options this way... so is this CAP always 0 for smmuv3's associated VIOMMU? There should be a "bool hw_nesting" flag (or some other name) in the SMMUState or SMMUDevice structure, that's set earlier by the support of nested HWPT allocation/invalidation and other factors. E.g. if "accel=on" is missing, set hw_nesting to false. Then SMMU's get_viommu_cap() callback function will simply check that flag. > or ... should intel-iommu follow this same/smmuv3 config option(s) and avoid this VIOMMU CAP req. ? We need this CAP for the vfio/pci core to allocate an S2 nesting parent HWPT. Thanks Nicolin