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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 00:40:22.2977 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0bac8a49-a55f-4885-beb8-08ddbe813018 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8261 Received-SPF: permerror client-ip=2a01:111:f403:2412::601; envelope-from=nicolinc@nvidia.com; helo=NAM10-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Jul 08, 2025 at 07:05:43AM -0400, Zhenzhong Duan wrote: > diff --git a/include/hw/iommu.h b/include/hw/iommu.h > new file mode 100644 > index 0000000000..e80aaf4431 > --- /dev/null > +++ b/include/hw/iommu.h > @@ -0,0 +1,16 @@ > +/* > + * General vIOMMU capabilities, flags, etc > + * > + * Copyright (C) 2025 Intel Corporation. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#ifndef HW_IOMMU_H > +#define HW_IOMMU_H > + > +enum { > + VIOMMU_CAP_STAGE1 = BIT_ULL(0), /* stage1 page table supported */ > +}; Thanks for this work. I am happy to see that we can share the common code that allocates a NESTING_PARENT in the core using this flag. Yet on ARM, a STAGE1 page table isn't always a nested S1, the hardware accelerated one. More often, it can be just a regular 1-stage translation table via emulated translation code and an emulated iotlb. I think this flag should indicate that the vIOMMU supports a HW-accelerated nested S1 HWPT allocation/invalidation. So, perhaps: /* hardware-accelerated nested stage-1 page table support */ VIOMMU_CAP_NESTED_S1 = BIT_ULL(0), ? Nicolin