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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014)(7416014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 19:20:37.7448 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 48558887-9359-4aac-9930-08ddbf1dafad X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8752 Received-SPF: permerror client-ip=40.107.243.57; envelope-from=nicolinc@nvidia.com; helo=NAM12-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Jul 09, 2025 at 01:55:46PM -0400, Donald Dutile wrote: > > > +enum { > > > + VIOMMU_CAP_STAGE1 = BIT_ULL(0), /* stage1 page table supported */ > > > +}; > > > > Thanks for this work. I am happy to see that we can share the > > common code that allocates a NESTING_PARENT in the core using > > this flag. > > > > Yet on ARM, a STAGE1 page table isn't always a nested S1, the > > hardware accelerated one. More often, it can be just a regular > > 1-stage translation table via emulated translation code and an > > emulated iotlb. > > > Because the user-created smmuv3 started as 'accelerated smmuv3', > and had been 'de-accelerated' to simply 'user created smmuv3', > I'm looking for some clarification in the above statement/request. > > Is the above suppose to reflect that a nested IOMMU has some hw-acceleration > in its Stage1 implementation? > If so, then call it that: STAGE1_ACCEL. > If it's suppose to represent that an IOMMU has nested/2-stage support, > then the above is a valid cap; -but-, having a nested/2-stage support IOMMU > doesn't necessarily mean its accelerated. Well, there are an emulated "nested" mode and an hw-accelerated "nested" mode in the smmuv3 code, so we had to choose something like "accel" over "nested". Here, on the other hand, I think the core using this CAP would unlikely care about an emulated "nested" mode in the individual vIOMMU.. So I suggested: /* hardware-accelerated nested stage-1 page table support */ VIOMMU_CAP_NESTED_S1 = BIT_ULL(0), which it should be clear IMHO. If not, maybe go a bit further like "VIOMMU_CAP_HW_NESTED_S1"? Thanks Nicolin