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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Junxiao Chang <junxiao.chang@intel.com>
Cc: <tomas.winkler@intel.com>,
	Jani Nikula <jani.nikula@linux.intel.com>,
	Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
	Tvrtko Ursulin <tursulin@ursulin.net>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
	"Clark Williams" <clrkwllms@kernel.org>,
	Steven Rostedt <rostedt@goodmis.org>,
	Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
	Vitaly Lubart <vitaly.lubart@intel.com>,
	Alexander Usyskin <alexander.usyskin@intel.com>,
	<intel-gfx@lists.freedesktop.org>,
	<dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>,
	<linux-rt-devel@lists.linux.dev>, <furong.zhou@intel.com>
Subject: Re: [PATCH] drm/i915/gsc: mei interrupt top half should be in irq disabled context
Date: Mon, 30 Jun 2025 14:22:45 -0400	[thread overview]
Message-ID: <aGLV9YL3EWXuf_Kk@intel.com> (raw)
In-Reply-To: <20250425151108.643649-1-junxiao.chang@intel.com>

On Fri, Apr 25, 2025 at 11:11:07PM +0800, Junxiao Chang wrote:
> MEI GSC interrupt comes from i915. It has top half and bottom half.
> Top half is called from i915 interrupt handler. It should be in
> irq disabled context.
> 
> With RT kernel, by default i915 IRQ handler is in threaded IRQ. MEI GSC
> top half might be in threaded IRQ context. generic_handle_irq_safe API
> could be called from either IRQ or process context, it disables local
> IRQ then calls MEI GSC interrupt top half.
> 
> This change fixes A380/A770 GPU boot hang issue with RT kernel.
> 
> Fixes: 1e3dc1d8622b ("drm/i915/gsc: add gsc as a mei auxiliary device")
> Tested-by: Furong Zhou <furong.zhou@intel.com>
> Suggested-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
> Signed-off-by: Junxiao Chang <junxiao.chang@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gsc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
> index 1e925c75fb080..c43febc862dc3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
> @@ -284,7 +284,7 @@ static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
>  	if (gt->gsc.intf[intf_id].irq < 0)
>  		return;
>  
> -	ret = generic_handle_irq(gt->gsc.intf[intf_id].irq);
> +	ret = generic_handle_irq_safe(gt->gsc.intf[intf_id].irq);


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
and pushed to drm-intel-gt-next

>  	if (ret)
>  		gt_err_ratelimited(gt, "error handling GSC irq: %d\n", ret);
>  }
> -- 
> 2.34.1
> 

  reply	other threads:[~2025-06-30 18:23 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-24  6:56 [PATCH] drm/i915/gsc: mei interrupt top half should be in irq disabled context Junxiao Chang
2025-04-24  7:15 ` Sebastian Andrzej Siewior
2025-04-24  7:30   ` Jani Nikula
2025-04-24 10:53     ` Chang, Junxiao
2025-04-24 11:07       ` Sebastian Andrzej Siewior
2025-04-24 13:39 ` ✓ i915.CI.BAT: success for " Patchwork
2025-04-24 20:37 ` ✗ i915.CI.Full: failure " Patchwork
2025-04-25  6:04 ` [PATCH] " Junxiao Chang
2025-04-25  8:00   ` Jani Nikula
2025-04-25  8:33     ` Chang, Junxiao
2025-04-25  8:27   ` Sebastian Andrzej Siewior
2025-04-25  7:29 ` ✗ i915.CI.BAT: failure for drm/i915/gsc: mei interrupt top half should be in irq disabled context (rev2) Patchwork
2025-04-25 12:04 ` [PATCH] drm/i915/gsc: mei interrupt top half should be in irq disabled context Junxiao Chang
2025-04-25 12:38   ` Sebastian Andrzej Siewior
2025-04-25 15:11 ` Junxiao Chang
2025-06-30 18:22   ` Rodrigo Vivi [this message]
2025-04-25 18:46 ` ✓ i915.CI.BAT: success for drm/i915/gsc: mei interrupt top half should be in irq disabled context (rev3) Patchwork
2025-04-25 19:38 ` ✓ i915.CI.BAT: success for drm/i915/gsc: mei interrupt top half should be in irq disabled context (rev4) Patchwork
2025-04-26  2:10 ` ✓ i915.CI.Full: " Patchwork

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