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Tsirkin" , Daniel P =?iso-8859-1?Q?=2E_Berrang=E9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: Re: [PATCH 03/16] i386/cpu: Add default cache model for Intel CPUs with level < 4 Message-ID: References: <20250620092734.1576677-1-zhao1.liu@intel.com> <20250620092734.1576677-4-zhao1.liu@intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: > > +/* > > + * Only used for the CPU models with CPUID level < 4. > > + * These CPUs (CPUID level < 4) only use CPUID leaf 2 to present > > + * cache information. > > + * > > + * Note: This cache model is just a default one, and is not > > + * guaranteed to match real hardwares. > > + */ > > +static const CPUCaches legacy_intel_cpuid2_cache_info = { > > + .l1d_cache = &(CPUCacheInfo) { > > + .type = DATA_CACHE, > > + .level = 1, > > + .size = 32 * KiB, > > + .self_init = 1, > > + .line_size = 64, > > + .associativity = 8, > > + .sets = 64, > > + .partitions = 1, > > + .no_invd_sharing = true, > > + .share_level = CPU_TOPOLOGY_LEVEL_CORE, > > + }, > > + .l1i_cache = &(CPUCacheInfo) { > > + .type = INSTRUCTION_CACHE, > > + .level = 1, > > + .size = 32 * KiB, > > + .self_init = 1, > > + .line_size = 64, > > + .associativity = 8, > > + .sets = 64, > > + .partitions = 1, > > + .no_invd_sharing = true, > > + .share_level = CPU_TOPOLOGY_LEVEL_CORE, > > + }, > > + .l2_cache = &(CPUCacheInfo) { > > + .type = UNIFIED_CACHE, > > + .level = 2, > > + .size = 2 * MiB, > > + .self_init = 1, > > + .line_size = 64, > > + .associativity = 8, > > + .sets = 4096, > > + .partitions = 1, > > + .no_invd_sharing = true, > > + .share_level = CPU_TOPOLOGY_LEVEL_CORE, > > + }, > > + .l3_cache = &(CPUCacheInfo) { > > + .type = UNIFIED_CACHE, > > + .level = 3, > > + .size = 16 * MiB, > > + .line_size = 64, > > + .associativity = 16, > > + .sets = 16384, > > + .partitions = 1, > > + .lines_per_tag = 1, > > + .self_init = true, > > + .inclusive = true, > > + .complex_indexing = true, > > + .share_level = CPU_TOPOLOGY_LEVEL_DIE, > > + }, > > Does this cache information match the real legacy HW or just an emulation > of Qemu? This is the pure emulation and it doesn't macth any HW :-(, and is a "hybrid" result of continuously modifying and adding new cache features (like the virtual L3). But for compatibility reasons, I abstracte it into this special cache model, used only for older CPUs. This way, at least modern CPUs won't be burdened by old historical issues. Thanks, Zhao