From: Zhao Liu <zhao1.liu@intel.com>
To: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Daniel P . Berrangé" <berrange@redhat.com>,
"Igor Mammedov" <imammedo@redhat.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Babu Moger" <babu.moger@amd.com>,
"Ewan Hai" <ewanhai-oc@zhaoxin.com>, "Pu Wen" <puwen@hygon.cn>,
"Tao Su" <tao1.su@intel.com>, "Yi Lai" <yi1.lai@intel.com>,
"Dapeng Mi" <dapeng1.mi@intel.com>,
qemu-devel@nongnu.org, kvm@vger.kernel.org
Subject: Re: [PATCH 01/16] i386/cpu: Refine comment of CPUID2CacheDescriptorInfo
Date: Thu, 3 Jul 2025 15:38:26 +0800 [thread overview]
Message-ID: <aGYzcgbyJglePNHF@intel.com> (raw)
In-Reply-To: <4fde6b82-0d13-48d8-898a-e105b9a79858@linux.intel.com>
> > + /*
> > + * Newer Intel CPUs (having the cores without L3, e.g., Intel MTL, ARL)
> > + * use CPUID 0x4 leaf to describe cache topology, by encoding CPUID 0x2
> > + * leaf with 0xFF. For older CPUs (without 0x4 leaf), it's also valid
> > + * to just ignore l3's code if there's no l3.
>
> s/l3/L3/g
Sure!
> Others look good to me.
>
> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Thanks!
next prev parent reply other threads:[~2025-07-03 7:17 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-20 9:27 [PATCH 00/16] i386/cpu: Unify the cache model in X86CPUState Zhao Liu
2025-06-20 9:27 ` [PATCH 01/16] i386/cpu: Refine comment of CPUID2CacheDescriptorInfo Zhao Liu
2025-07-02 8:48 ` Mi, Dapeng
2025-07-03 7:38 ` Zhao Liu [this message]
2025-06-20 9:27 ` [PATCH 02/16] i386/cpu: Add descriptor 0x49 for CPUID 0x2 encoding Zhao Liu
2025-07-02 9:04 ` Mi, Dapeng
2025-07-03 7:39 ` Zhao Liu
2025-06-20 9:27 ` [PATCH 03/16] i386/cpu: Add default cache model for Intel CPUs with level < 4 Zhao Liu
2025-07-02 9:53 ` Mi, Dapeng
2025-07-03 7:47 ` Zhao Liu
2025-06-20 9:27 ` [PATCH 04/16] i386/cpu: Present same cache model in CPUID 0x2 & 0x4 Zhao Liu
2025-07-03 4:14 ` Mi, Dapeng
2025-07-03 6:35 ` Mi, Dapeng
2025-06-20 9:27 ` [PATCH 05/16] i386/cpu: Consolidate CPUID 0x4 leaf Zhao Liu
2025-06-26 12:10 ` Ewan Hai
2025-06-27 2:44 ` Zhao Liu
2025-07-03 6:41 ` Mi, Dapeng
2025-06-20 9:27 ` [PATCH 06/16] i386/cpu: Drop CPUID 0x2 specific cache info in X86CPUState Zhao Liu
2025-07-03 7:03 ` Mi, Dapeng
2025-06-20 9:27 ` [PATCH 07/16] i386/cpu: Mark CPUID[0x80000005] as reserved for Intel Zhao Liu
2025-07-03 7:07 ` Mi, Dapeng
2025-06-20 9:27 ` [PATCH 08/16] i386/cpu: Fix CPUID[0x80000006] for Intel CPU Zhao Liu
2025-07-03 7:09 ` Mi, Dapeng
2025-07-03 7:52 ` Zhao Liu
2025-06-20 9:27 ` [PATCH 09/16] i386/cpu: Add legacy_intel_cache_info cache model Zhao Liu
2025-07-03 7:15 ` Mi, Dapeng
2025-06-20 9:27 ` [PATCH 10/16] i386/cpu: Add legacy_amd_cache_info " Zhao Liu
2025-07-03 7:18 ` Mi, Dapeng
2025-06-20 9:27 ` [PATCH 11/16] i386/cpu: Select legacy cache model based on vendor in CPUID 0x2 Zhao Liu
2025-07-03 8:47 ` Mi, Dapeng
2025-06-20 9:27 ` [PATCH 12/16] i386/cpu: Select legacy cache model based on vendor in CPUID 0x4 Zhao Liu
2025-07-03 8:49 ` Mi, Dapeng
2025-06-20 9:27 ` [PATCH 13/16] i386/cpu: Select legacy cache model based on vendor in CPUID 0x80000005 Zhao Liu
2025-07-03 8:52 ` Mi, Dapeng
2025-06-20 9:27 ` [PATCH 14/16] i386/cpu: Select legacy cache model based on vendor in CPUID 0x80000006 Zhao Liu
2025-06-20 9:27 ` [PATCH 15/16] i386/cpu: Select legacy cache model based on vendor in CPUID 0x8000001D Zhao Liu
2025-06-20 9:27 ` [PATCH 16/16] i386/cpu: Use a unified cache_info in X86CPUState Zhao Liu
2025-07-03 8:53 ` Mi, Dapeng
2025-07-03 9:50 ` Zhao Liu
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