From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 292631CD1F for ; Thu, 3 Jul 2025 07:18:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751527082; cv=none; b=MeNXMcjboCsbXIIMHxNEmpJzNK260qI9gH58mKqbAH2i5nlTODy71UpAaN+eqFn7Sq5iPlq0I8C/hrdsRV+uosvseIe/EE5M7XbNGn8JBVUTNBXgX72iICsEBuMrGaLFOMaUx8RyblDhXiJfuxIYebON8zf5GLdrpHuMfbGFERQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751527082; c=relaxed/simple; bh=gVSmDn6dadFMZFYmEeJHA7ecHxg6HSPxUgwGHWgIW4Y=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=kYhqjt7QknaGxKsfvNxbJQRCuvTIbPzffkZee5xnYs8SDJDbbZNbM/V3JH5icvd9uZIbukdaajutWrfZiv6eQZOxQA6K+ReNO46CXtfF1Flld96SBBt6r9cD4Nd9bnFaGqk4bY7oTW8UGfCfOM1drZG6+ENpCS5qlAGbVaLUHHM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WxQ+iKHd; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WxQ+iKHd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751527081; x=1783063081; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=gVSmDn6dadFMZFYmEeJHA7ecHxg6HSPxUgwGHWgIW4Y=; b=WxQ+iKHdHT0RwA0BucrRCYxIZ3/YUoTXn5DcnLrxUCRmoxzUC7O/oslk sgUcVBiBKHaC7jleAf6TBxo27hfxmGsDC5fChYzzxD4/bJzDuS8KThipv YUJ2ONxule2UXhscJhttFV6Jql7THeuJTwZhPbfSvS4gpdA/UW8FfTjTF ToPlk82CMmkBvGpl+Hi2CV0BAeMGCQ1V62nZGEmuk5H3ouBFQpuZ8jjqu Prsg5mwLRVFyPpbGkId/KvpX3qXmqG3jIrEzGXPYdicFe+/VIj1K7uORY v9vW1zjgB21DKKjK/x2HJmkhj4767JjxqWmXzC+yNtL5e87SymhkZwSgf g==; X-CSE-ConnectionGUID: nwXFStRZTee03CHW9dVn9w== X-CSE-MsgGUID: EqlSMfgNSWuov4YHIwtHxA== X-IronPort-AV: E=McAfee;i="6800,10657,11482"; a="65188063" X-IronPort-AV: E=Sophos;i="6.16,283,1744095600"; d="scan'208";a="65188063" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2025 00:18:00 -0700 X-CSE-ConnectionGUID: FAI4D8/oQSOLWFQ72zhtSw== X-CSE-MsgGUID: JxEFckacSomB8SdkLRZXiA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,283,1744095600"; d="scan'208";a="185229199" Received: from liuzhao-optiplex-7080.sh.intel.com (HELO localhost) ([10.239.160.39]) by fmviesa001.fm.intel.com with ESMTP; 03 Jul 2025 00:17:56 -0700 Date: Thu, 3 Jul 2025 15:39:22 +0800 From: Zhao Liu To: "Mi, Dapeng" Cc: Paolo Bonzini , Marcelo Tosatti , "Michael S . Tsirkin" , Daniel P =?iso-8859-1?Q?=2E_Berrang=E9?= , Igor Mammedov , Marcel Apfelbaum , Richard Henderson , Eduardo Habkost , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Babu Moger , Ewan Hai , Pu Wen , Tao Su , Yi Lai , Dapeng Mi , qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: Re: [PATCH 02/16] i386/cpu: Add descriptor 0x49 for CPUID 0x2 encoding Message-ID: References: <20250620092734.1576677-1-zhao1.liu@intel.com> <20250620092734.1576677-3-zhao1.liu@intel.com> <0b2a6fbe-6232-4e6a-8423-ab09f6d312b7@linux.intel.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <0b2a6fbe-6232-4e6a-8423-ab09f6d312b7@linux.intel.com> > > - /* Descriptor 0x49 depends on CPU family/model, so it is not included */ > > + /* > > + * Descriptor 0x49 has 2 cases: > > + * - 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size. > > + * - 3rd-level cache: 4MB, 16-way set associative, 64-byte line size > > + * (Intel Xeon processor MP, Family 0FH, Model 06H). > > + * > > + * When it represents l3, then it depends on CPU family/model. Fortunately, > > + * the legacy cache/CPU models don't have such special l3. So, just add it > > + * to represent the general l2 case. > > For comments and commit message, we'd better use the capital character > "L2/L3" to represent the 2nd/3rd level cache which is more conventional.  Sure. > Others look good to me. > > Reviewed-by: Dapeng Mi Thanks!