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From: Itaru Kitayama To: Jonathan Cameron Cc: qemu-devel@nongnu.org, Fan Ni , Peter Maydell , Eric Auger , mst@redhat.com, Zhijian Li , linuxarm@huawei.com, linux-cxl@vger.kernel.org, qemu-arm@nongnu.org, Yuquan Wang , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Alex =?iso-8859-1?Q?Benn=E9e?= Subject: Re: [PATCH qemu v17 5/5] qtest/cxl: Add aarch64 virt test for CXL Message-ID: References: <20250703104110.992379-1-Jonathan.Cameron@huawei.com> <20250703104110.992379-6-Jonathan.Cameron@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250703104110.992379-6-Jonathan.Cameron@huawei.com> X-Migadu-Flow: FLOW_OUT On Thu, Jul 03, 2025 at 11:41:10AM +0100, Jonathan Cameron wrote: > Add a single complex case for aarch64 virt machine. > > Given existing much more comprehensive tests for x86 cover the common > functionality, a single test should be enough to verify that the aarch64 > part continues to work. > > Tested-by: Itaru Kitayama > Reviewed-by: Eric Auger > Signed-off-by: Jonathan Cameron > > --- > v17: Tag and small fix for patch description (Eric). > --- > tests/qtest/cxl-test.c | 58 ++++++++++++++++++++++++++++++++--------- > tests/qtest/meson.build | 1 + > 2 files changed, 46 insertions(+), 13 deletions(-) > > diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c > index a600331843..8fb7e58d4f 100644 > --- a/tests/qtest/cxl-test.c > +++ b/tests/qtest/cxl-test.c > @@ -19,6 +19,12 @@ > "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " > > +#define QEMU_VIRT_2PXB_CMD \ > + "-machine virt,cxl=on -cpu max " \ > + "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \ > + "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \ > + "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G " > + > #define QEMU_RP \ > "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " > > @@ -197,25 +203,51 @@ static void cxl_2pxb_4rp_4t3d(void) > qtest_end(); > rmdir(tmpfs); > } > + > +static void cxl_virt_2pxb_4rp_4t3d(void) > +{ > + g_autoptr(GString) cmdline = g_string_new(NULL); > + g_autofree const char *tmpfs = NULL; > + > + tmpfs = g_dir_make_tmp("cxl-test-XXXXXX", NULL); > + > + g_string_printf(cmdline, QEMU_VIRT_2PXB_CMD QEMU_4RP QEMU_4T3D, > + tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, > + tmpfs, tmpfs); > + > + qtest_start(cmdline->str); > + qtest_end(); > + rmdir(tmpfs); > +} > #endif /* CONFIG_POSIX */ > > int main(int argc, char **argv) > { > - g_test_init(&argc, &argv, NULL); > + const char *arch = qtest_get_arch(); > > - qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); > - qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); > - qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); > - qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); > - qtest_add_func("/pci/cxl/rp", cxl_root_port); > - qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); > + g_test_init(&argc, &argv, NULL); > + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { > + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); > + qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); > + qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); > + qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); > + qtest_add_func("/pci/cxl/rp", cxl_root_port); > + qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); > #ifdef CONFIG_POSIX > - qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); > - qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); > - qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); > - qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa); > - qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); > - qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d); > + qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); > + qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); > + qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); > + qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa); > + qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); > + qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", > + cxl_2pxb_4rp_4t3d); > #endif > + } else if (strcmp(arch, "aarch64") == 0) { > +#ifdef CONFIG_POSIX > + qtest_add_func("/pci/cxl/virt/pxb_x2_root_port_x4_type3_x4", > + cxl_virt_2pxb_4rp_4t3d); > +#endif > + } > + > return g_test_run(); > } > diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build > index 8ad849054f..42e927b32a 100644 > --- a/tests/qtest/meson.build > +++ b/tests/qtest/meson.build > @@ -261,6 +261,7 @@ qtests_aarch64 = \ > config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \ > (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : []) + \ > (config_all_devices.has_key('CONFIG_NPCM8XX') ? qtests_npcm8xx : []) + \ > + qtests_cxl + \ > ['arm-cpu-features', > 'numa-test', > 'boot-serial-test', > -- I checked out jic23/cxl-2025-07-03 branch and built fine for all the architectures, and did `meson test qtest-aarch64/cxl-test` returned OK. Again, for the latest v17 Tested-by: Itaru Kitayama Thanks, Itaru. > 2.48.1 >