From: Francois Dugast <francois.dugast@intel.com>
To: "Zbigniew Kempczyński" <zbigniew.kempczynski@intel.com>
Cc: <igt-dev@lists.freedesktop.org>
Subject: Re: [PATCH i-g-t 2/3] lib/intel_compute: use macros instead of binary data in post-sync op
Date: Fri, 4 Jul 2025 10:01:46 +0200 [thread overview]
Message-ID: <aGeKakU90Ua2Pw5n@fdugast-desk> (raw)
In-Reply-To: <20250703063032.553963-7-zbigniew.kempczynski@intel.com>
On Thu, Jul 03, 2025 at 08:30:35AM +0200, Zbigniew Kempczyński wrote:
> Upcoming change in TG preemption detection requires modification in
> compute-walker post-sync write. Replace binary post-sync to macros
> which are easier to read and modify.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Francois Dugast <francois.dugast@intel.com>
LGTM according to bspecs:
Reviewed-by: Francois Dugast <francois.dugast@intel.com>
> ---
> lib/intel_compute.c | 40 +++++++++++++++++++++++++++++-----------
> 1 file changed, 29 insertions(+), 11 deletions(-)
>
> diff --git a/lib/intel_compute.c b/lib/intel_compute.c
> index 9f5fc1bc59..9549b58fdf 100644
> --- a/lib/intel_compute.c
> +++ b/lib/intel_compute.c
> @@ -14,6 +14,7 @@
> #include "gen8_media.h"
> #include "gen9_media.h"
> #include "intel_compute.h"
> +#include "intel_mocs.h"
> #include "lib/igt_syncobj.h"
> #include "lib/intel_reg.h"
> #include "xe/xe_ioctl.h"
> @@ -60,6 +61,9 @@
> #define ENQUEUED_LOCAL_SIZE_X 1024
> #define ENQUEUED_LOCAL_SIZE_Y 1
> #define ENQUEUED_LOCAL_SIZE_Z 1
> +#define DP_SS_CACHE_FLUSH (1 << 12)
> +#define DP_PIPELINE_FLUSH (1 << 2)
> +#define WRITE_TIMESTAMP (3 << 0)
>
> /*
> * TGP - ThreadGroup Preemption
> @@ -975,7 +979,8 @@ static void xehp_create_surface_state(uint32_t *addr_bo_buffer_batch,
> addr_bo_buffer_batch[b++] = 0x00000000;
> }
>
> -static void xehp_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
> +static void xehp_compute_exec_compute(int fd,
> + uint32_t *addr_bo_buffer_batch,
> uint64_t addr_general_state_base,
> uint64_t addr_surface_state_base,
> uint64_t addr_dynamic_state_base,
> @@ -983,6 +988,7 @@ static void xehp_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
> uint64_t offset_indirect_data_start,
> uint64_t kernel_start_pointer)
> {
> + uint8_t wb_mocs = intel_get_wb_mocs_index(fd);
> int b = 0;
>
> igt_debug("general state base: %"PRIx64"\n", addr_general_state_base);
> @@ -1067,7 +1073,8 @@ static void xehp_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
>
> addr_bo_buffer_batch[b++] = 0x00000008;
> addr_bo_buffer_batch[b++] = 0x00000000;
> - addr_bo_buffer_batch[b++] = 0x00001027;
> + addr_bo_buffer_batch[b++] = DP_SS_CACHE_FLUSH | wb_mocs << 4 |
> + DP_PIPELINE_FLUSH | WRITE_TIMESTAMP;
> addr_bo_buffer_batch[b++] = ADDR_BATCH;
> addr_bo_buffer_batch[b++] = ADDR_BATCH >> 32;
> addr_bo_buffer_batch[b++] = 0x00000000;
> @@ -1150,7 +1157,8 @@ static void xehp_compute_exec(int fd, const unsigned char *kernel,
> input_data = get_input_data(&execenv, user, bo_dict[4].data);
> output_data = get_output_data(&execenv, user, bo_dict[5].data);
>
> - xehp_compute_exec_compute(bo_dict[8].data,
> + xehp_compute_exec_compute(fd,
> + bo_dict[8].data,
> ADDR_GENERAL_STATE_BASE,
> ADDR_SURFACE_STATE_BASE,
> ADDR_DYNAMIC_STATE_BASE,
> @@ -1201,7 +1209,8 @@ static void xehpc_create_indirect_data(uint32_t *addr_bo_buffer_batch,
> addr_bo_buffer_batch[b++] = ENQUEUED_LOCAL_SIZE_Z;
> }
>
> -static void xehpc_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
> +static void xehpc_compute_exec_compute(int fd,
> + uint32_t *addr_bo_buffer_batch,
> uint64_t addr_general_state_base,
> uint64_t addr_surface_state_base,
> uint64_t addr_dynamic_state_base,
> @@ -1209,6 +1218,7 @@ static void xehpc_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
> uint64_t offset_indirect_data_start,
> uint64_t kernel_start_pointer)
> {
> + uint8_t wb_mocs = intel_get_wb_mocs_index(fd);
> int b = 0;
>
> igt_debug("general state base: %"PRIx64"\n", addr_general_state_base);
> @@ -1293,7 +1303,8 @@ static void xehpc_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
>
> addr_bo_buffer_batch[b++] = 0x00000008;
> addr_bo_buffer_batch[b++] = 0x00000000;
> - addr_bo_buffer_batch[b++] = 0x00001047;
> + addr_bo_buffer_batch[b++] = DP_SS_CACHE_FLUSH | wb_mocs << 4 |
> + DP_PIPELINE_FLUSH | WRITE_TIMESTAMP;
> addr_bo_buffer_batch[b++] = ADDR_BATCH;
> addr_bo_buffer_batch[b++] = ADDR_BATCH >> 32;
> addr_bo_buffer_batch[b++] = 0x00000000;
> @@ -1364,7 +1375,8 @@ static void xehpc_compute_exec(int fd, const unsigned char *kernel,
> input_data = get_input_data(&execenv, user, bo_dict[2].data);
> output_data = get_output_data(&execenv, user, bo_dict[3].data);
>
> - xehpc_compute_exec_compute(bo_dict[5].data,
> + xehpc_compute_exec_compute(fd,
> + bo_dict[5].data,
> ADDR_GENERAL_STATE_BASE,
> ADDR_SURFACE_STATE_BASE,
> ADDR_DYNAMIC_STATE_BASE,
> @@ -1532,7 +1544,8 @@ static void xelpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
> addr_bo_buffer_batch[b++] = MI_BATCH_BUFFER_END;
> }
>
> -static void xe2lpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
> +static void xe2lpg_compute_exec_compute(int fd,
> + uint32_t *addr_bo_buffer_batch,
> uint64_t addr_general_state_base,
> uint64_t addr_surface_state_base,
> uint64_t addr_dynamic_state_base,
> @@ -1544,6 +1557,7 @@ static void xe2lpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
> bool threadgroup_preemption,
> uint32_t work_size)
> {
> + uint8_t wb_mocs = intel_get_wb_mocs_index(fd);
> int b = 0;
>
> igt_debug("general state base: %"PRIx64"\n", addr_general_state_base);
> @@ -1651,7 +1665,8 @@ static void xe2lpg_compute_exec_compute(uint32_t *addr_bo_buffer_batch,
> addr_bo_buffer_batch[b++] = 0x0c000000 | THREADS_PER_GROUP;
> addr_bo_buffer_batch[b++] = 0x00000000;
> addr_bo_buffer_batch[b++] = 0x00000000;
> - addr_bo_buffer_batch[b++] = 0x00001047;
> + addr_bo_buffer_batch[b++] = DP_SS_CACHE_FLUSH | wb_mocs << 4 |
> + DP_PIPELINE_FLUSH | WRITE_TIMESTAMP;
> addr_bo_buffer_batch[b++] = ADDR_BATCH;
> addr_bo_buffer_batch[b++] = ADDR_BATCH >> 32;
> addr_bo_buffer_batch[b++] = 0x00000000;
> @@ -1857,7 +1872,8 @@ static void xe2lpg_compute_exec(int fd, const unsigned char *kernel,
> input_data = get_input_data(&execenv, user, bo_dict[4].data);
> output_data = get_output_data(&execenv, user, bo_dict[5].data);
>
> - xe2lpg_compute_exec_compute(bo_dict[8].data,
> + xe2lpg_compute_exec_compute(fd,
> + bo_dict[8].data,
> ADDR_GENERAL_STATE_BASE,
> ADDR_SURFACE_STATE_BASE,
> ADDR_DYNAMIC_STATE_BASE,
> @@ -2152,13 +2168,15 @@ static void xe2lpg_compute_preempt_exec(int fd, const unsigned char *long_kernel
>
> bo_randomize(input_short, SIZE_DATA);
>
> - xe2lpg_compute_exec_compute(bo_dict_long[8].data, ADDR_GENERAL_STATE_BASE,
> + xe2lpg_compute_exec_compute(fd,
> + bo_dict_long[8].data, ADDR_GENERAL_STATE_BASE,
> ADDR_SURFACE_STATE_BASE, ADDR_DYNAMIC_STATE_BASE,
> ADDR_INSTRUCTION_STATE_BASE, XE2_ADDR_STATE_CONTEXT_DATA_BASE,
> OFFSET_INDIRECT_DATA_START, OFFSET_KERNEL, OFFSET_STATE_SIP,
> threadgroup_preemption, SIZE_DATA);
>
> - xe2lpg_compute_exec_compute(bo_dict_short[8].data, ADDR_GENERAL_STATE_BASE,
> + xe2lpg_compute_exec_compute(fd,
> + bo_dict_short[8].data, ADDR_GENERAL_STATE_BASE,
> ADDR_SURFACE_STATE_BASE, ADDR_DYNAMIC_STATE_BASE,
> ADDR_INSTRUCTION_STATE_BASE, XE2_ADDR_STATE_CONTEXT_DATA_BASE,
> OFFSET_INDIRECT_DATA_START, OFFSET_KERNEL, OFFSET_STATE_SIP,
> --
> 2.43.0
>
next prev parent reply other threads:[~2025-07-04 8:02 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-03 6:30 [PATCH i-g-t 0/3] TG preemption detection improvements Zbigniew Kempczyński
2025-07-03 6:30 ` [PATCH i-g-t 1/3] lib/intel_mocs: fix wb mocs entry for MTL Zbigniew Kempczyński
2025-07-03 8:41 ` Matthew Auld
2025-07-03 6:30 ` [PATCH i-g-t 2/3] lib/intel_compute: use macros instead of binary data in post-sync op Zbigniew Kempczyński
2025-07-04 8:01 ` Francois Dugast [this message]
2025-07-03 6:30 ` [PATCH i-g-t 3/3] lib/intel_compute: use post-sync write to detect command level preemption Zbigniew Kempczyński
2025-07-04 8:02 ` Francois Dugast
2025-07-04 8:05 ` Zbigniew Kempczyński
2025-07-03 8:02 ` ✗ Xe.CI.BAT: failure for TG preemption detection improvements Patchwork
2025-07-03 10:41 ` Zbigniew Kempczyński
2025-07-03 8:05 ` ✓ i915.CI.BAT: success " Patchwork
2025-07-03 11:48 ` ✓ Xe.CI.BAT: " Patchwork
2025-07-03 15:38 ` ✗ i915.CI.Full: failure " Patchwork
2025-07-04 21:12 ` ✗ Xe.CI.Full: " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aGeKakU90Ua2Pw5n@fdugast-desk \
--to=francois.dugast@intel.com \
--cc=igt-dev@lists.freedesktop.org \
--cc=zbigniew.kempczynski@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.