Re: [PATCH] i386/cpu: Remove FEAT_24_0_EBX for AVX10

[Zhao Liu <zhao1.liu@intel.com>]

On Fri, Jul 04, 2025 at 10:45:04PM +0800, Xiaoyao Li wrote:
> Date: Fri, 4 Jul 2025 22:45:04 +0800
> From: Xiaoyao Li <xiaoyao.li@intel.com>
> Subject: [PATCH] i386/cpu: Remove FEAT_24_0_EBX for AVX10
> X-Mailer: git-send-email 2.43.0
> 
> Intel AVX10 spec has been updated to make the bit 16-18 of
  ^^^^^^^^^^^^^^^^

This "AVX10 spec" is misleading, there are both AVX10.1 spec and AVX10.2
spec, and QEMU currently supports AVX10.1 for the GNR, but your change
is based on AVX10.2 spec.

It would be good to explain something like,

Although AVX10.1 has already marked AVX10/128 as always supported in
revision 3.1 (QEMU did not synchronize this change), in the latest
AVX10.2 spec (revison 5.0), AVX10 roadmap is updated, "AVX10/512 will be
used in all Intel products, supporting vector lengths of 128, 256, and
512 in all product lines". This applies for all AVX10 versions.

> CPUID.24_0.EBX as reserved at 1 because all the Intel processors with
> AVX10 support will support all the vector lengths.
>
> The bits will be reserved at 1 to ensure the compatibility of the
> existing software. For QEMU, it makes no sense to allow the
> configurability of the bits anymore. So just remove the leaf
> FEAT_24_0_EBX and related stuff and hardcore the bits to all 1 when
> AVX10 is exposed to guest.

Add the doc link here if thers's next version.

> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
> ---
>  target/i386/cpu.c | 36 +-----------------------------------
>  target/i386/cpu.h | 12 ------------
>  2 files changed, 1 insertion(+), 47 deletions(-)

...

> @@ -7720,7 +7686,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>          *ecx = 0;
>          *edx = 0;
>          if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count == 0) {
> -            *ebx = env->features[FEAT_24_0_EBX] | env->avx10_version;
> +            *ebx = (0x7U << 16) | env->avx10_version;

Instead of hardcode, it's better to keep the macros and encoded this
like:

*ebx = CPUID_24_0_EBX_AVX10_VL_MASK | env->avx10_version;

and leave a comment: all processors supporting Intel AVX10 will include
support for all vector lengths.

>          }
>          break;
>      }