Re: [PATCH v2] i386/cpu: Remove FEAT_24_0_EBX for AVX10

[Zhao Liu <zhao1.liu@intel.com>]

On Mon, Jul 07, 2025 at 10:11:51PM +0800, Xiaoyao Li wrote:
> Date: Mon, 7 Jul 2025 22:11:51 +0800
> From: Xiaoyao Li <xiaoyao.li@intel.com>
> Subject: [PATCH v2] i386/cpu: Remove FEAT_24_0_EBX for AVX10
> X-Mailer: git-send-email 2.43.0
> 
> It turns out that all the Intel processors enumerating the support of
> Intel AVX10 support all vector widths. It's documented in the latest
> SDM, vol 1, Chapter 16 "programming with Intel AVX10".
> 
> (Note that AVX10.1 spec stops update since AVX10 is subsumed into SDM
>  while AVX10.2 spec stays update for the future extension of AVX10)
> 
> Now SDM [1] marks the bit 16-18 of CPUID.0x24_0.EBX as reserved and they
> are reserved at 1. The purpose of Intel is to remove the semantic of
> vector length enumeration from these bits since all the 128/256/512 bit
> length are supported and no need for enumeration. But Intel has to keep
> them reserved at 1 to make it compatible with the software written based
> on earlier avx10 spec that checks the bits to query of the support of each
> vector length.
> 
> For QEMU, it makes no sense to allow the configurability of the bits
> anymore. Remove the leaf FEAT_24_0_EBX and related stuff. Just hardcore
> the bits to all 1 when AVX10 is exposed to guest, to comply with the SDM
> and stop trying to associate them with the enumeration of vector length.
> 
> [1] https://cdrdv2.intel.com/v1/dl/getContent/671200 (rev 088)
> 
> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
> ---
> changes in v2:
>  - refine the commit message to reference update from SDM instead of
>    AVX10 spec;
>  - call out explicitly the purpose of disassociating the enumeration of
>    vector length from the CPUID bits.
> ---
>  target/i386/cpu.c | 37 ++-----------------------------------
>  target/i386/cpu.h | 12 ------------
>  2 files changed, 2 insertions(+), 47 deletions(-)

LGTM,

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>