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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 22:59:36.5831 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7d86735a-6213-461b-488e-08ddc0057173 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F65.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9260 Received-SPF: permerror client-ip=2a01:111:f403:2009::61f; envelope-from=nicolinc@nvidia.com; helo=NAM10-BN7-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Tue, Jul 08, 2025 at 04:40:50PM +0100, Shameer Kolothum wrote: > Currently, pci_setup_iommu() registers IOMMU ops for a given PCIBus. > However, when retrieving IOMMU ops for a device using > pci_device_get_iommu_bus_devfn(), the function checks the parent_dev > and fetches IOMMU ops from the parent device, even if the current > bus does not have any associated IOMMU ops. > > This behavior works for now because QEMU's IOMMU implementations are > globally scoped, and host bridges rely on the bypass_iommu property > to skip IOMMU translation when needed. > > However, this model will break with the soon to be introduced > arm-smmuv3 device, which allows users to associate the IOMMU > with a specific PCIe root complex (e.g., the default pcie.0 > or a pxb-pcie root complex). > > For example, consider the following setup with multiple root > complexes: > > -device arm-smmuv3,primary-bus=pcie.0,id=smmuv3.0 \ > ... > -device pxb-pcie,id=pcie.1,bus_nr=8,bus=pcie.0 \ > -device pcie-root-port,id=pcie.port1,bus=pcie.1 \ > -device virtio-net-pci,bus=pcie.port1 > > In Qemu, pxb-pcie acts as a special root complex whose parent is > effectively the default root complex(pcie.0). Hence, though pcie.1 > has no associated SMMUv3 as per above, pci_device_get_iommu_bus_devfn() > will incorrectly return the IOMMU ops from pcie.0 due to the fallback > via parent_dev. > > To fix this, introduce a new helper pci_setup_iommu_per_bus() that > explicitly sets the new iommu_per_bus field in the PCIBus structure. > This helper will be used in a subsequent patch that adds support for > the new arm-smmuv3 device. > > Update pci_device_get_iommu_bus_devfn() to use iommu_per_bus when > determining the correct IOMMU ops, ensuring accurate behavior for > per-bus IOMMUs. > > Reviewed-by: Jonathan Cameron > Reviewed-by: Eric Auger > Tested-by: Nathan Chen > Tested-by: Eric Auger > Signed-off-by: Shameer Kolothum Reviewed-by: Nicolin Chen With a nit: > + /* > + * When multiple PCI Express Root Buses are defined using pxb-pcie, > + * the IOMMU configuration may be specific to each root bus. However, > + * pxb-pcie acts as a special root complex whose parent is effectively > + * the default root complex(pcie.0). Ensure that we retrieve the > + * correct IOMMU ops(if any) in such cases. > + */ > + if (pci_bus_is_express(iommu_bus) && pci_bus_is_root(iommu_bus)) { > + if (!iommu_bus->iommu_per_bus && parent_bus->iommu_per_bus) { > + break; > + } I think this should just check "if (parent_bus->iommu_per_bus)", which means that the parent's iommu bus is private so not shared with any other PCI buses.