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dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTPS id 56BApeFe051347 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=OK); Fri, 11 Jul 2025 18:51:40 +0800 (+08) (envelope-from ben717@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 11 Jul 2025 18:51:40 +0800 Date: Fri, 11 Jul 2025 18:51:40 +0800 From: Ben Zong-You Xie To: "Lad, Prabhakar" CC: , , , , , , , , , , , , , , , Subject: Re: [PATCH 1/8] riscv: add Andes SoC family Kconfig support Message-ID: References: <20250704081451.2011407-1-ben717@andestech.com> <20250704081451.2011407-2-ben717@andestech.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/2.1.4 (2021-12-11) X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 56BApeFe051347 On Mon, Jul 07, 2025 at 10:50:38AM +0100, Lad, Prabhakar wrote: > [EXTERNAL MAIL] > > Hi Ben, > > Thank you for the patch. > > On Fri, Jul 4, 2025 at 10:02 AM Ben Zong-You Xie wrote: > > > > The first SoC in the Andes series is QiLai. It includes a high-performance > > quad-core RISC-V AX45MP cluster and one NX27V vector processor. > > > > For further information, refer to [1]. > > > > [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/ > > > > Signed-off-by: Ben Zong-You Xie > > --- > > arch/riscv/Kconfig.errata | 2 +- > > arch/riscv/Kconfig.socs | 9 +++++++++ > > 2 files changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata > > index e318119d570d..be76883704a6 100644 > > --- a/arch/riscv/Kconfig.errata > > +++ b/arch/riscv/Kconfig.errata > > @@ -12,7 +12,7 @@ config ERRATA_ANDES > > > > config ERRATA_ANDES_CMO > > bool "Apply Andes cache management errata" > > - depends on ERRATA_ANDES && ARCH_R9A07G043 > > + depends on ERRATA_ANDES && (ARCH_R9A07G043 || ARCH_ANDES) > > select RISCV_DMA_NONCOHERENT > > default y > > help > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > > index a9c3d2f6debc..1bf5637f2601 100644 > > --- a/arch/riscv/Kconfig.socs > > +++ b/arch/riscv/Kconfig.socs > > @@ -1,5 +1,14 @@ > > menu "SoC selection" > > > > +config ARCH_ANDES > > + bool "Andes SoCs" > > + depends on MMU && !XIP_KERNEL > > + select ERRATA_ANDES > > + select ERRATA_ANDES_CMO > > + select AX45MP_L2_CACHE > Do all the Andes SoCs require all the above three configs? (If not I > would add it based on the SoC which requires it.) > Hi Prabhakar, Thanks for your suggestion. QiLai SoC does not need below two configs since it has IOCP. I will remove below two configs in the next version. Thanks, Ben