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Fri, 11 Jul 2025 17:38:18 -0700 (PDT) Received: from localhost ([2a00:79e0:2e14:7:2386:8bd3:333b:b774]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-74eb9f8bd3bsm6429988b3a.149.2025.07.11.17.38.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Jul 2025 17:38:17 -0700 (PDT) Date: Fri, 11 Jul 2025 17:38:16 -0700 From: Brian Norris To: Manivannan Sadhasivam Cc: Bartosz Golaszewski , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Krishna Chaitanya Chundru Subject: Re: [PATCH RFC 2/3] PCI/pwrctrl: Allow pwrctrl core to control PERST# GPIO if available Message-ID: References: <20250707-pci-pwrctrl-perst-v1-0-c3c7e513e312@kernel.org> <20250707-pci-pwrctrl-perst-v1-2-c3c7e513e312@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250707-pci-pwrctrl-perst-v1-2-c3c7e513e312@kernel.org> Sorry for so many individual reviews, but I've passed over this a few times and had new questions/comments several times: On Mon, Jul 07, 2025 at 11:48:39PM +0530, Manivannan Sadhasivam wrote: > PERST# is an (optional) auxiliary signal provided by the PCIe host to > components for signalling 'Fundamental Reset' as per the PCIe spec r6.0, > sec 6.6.1. > void pci_pwrctrl_init(struct pci_pwrctrl *pwrctrl, struct device *dev) > { > + struct pci_host_bridge *host_bridge = to_pci_host_bridge(dev->parent); > + int devfn; > + > pwrctrl->dev = dev; > INIT_WORK(&pwrctrl->work, rescan_work_func); > + > + if (!host_bridge->perst) > + return; > + > + devfn = of_pci_get_devfn(dev_of_node(dev)); > + if (devfn >= 0 && host_bridge->perst[PCI_SLOT(devfn)]) This seems to imply a 1:1 correlation between slots and pwrctrl devices, almost as if you expect everyone is using drivers/pci/pwrctrl/slot.c. But there is also endpoint-specific pwrctrl support, and there's quite a bit of flexibility around what these hierarchies can look like. How do you account for that? For example, couldn't you have both a "port" and an "endpoint" pwrctrl? Would they both grab the same PERST# GPIO here? And might that incur excessive resets, possibly even clobbering each other? Or what if multiple slots are governed by a single GPIO? Do you expect the bridge perst[] array to contain redundant GPIOs? Brian > + pwrctrl->perst = host_bridge->perst[PCI_SLOT(devfn)]; > } > EXPORT_SYMBOL_GPL(pci_pwrctrl_init);