Re: [PATCH v2 1/2] target/i386: Add TSA attack variants TSA-SQ and TSA-L1

[Zhao Liu <zhao1.liu@intel.com>]

On Thu, Jul 10, 2025 at 02:46:10PM -0500, Babu Moger wrote:
> Date: Thu, 10 Jul 2025 14:46:10 -0500
> From: Babu Moger <babu.moger@amd.com>
> Subject: [PATCH v2 1/2] target/i386: Add TSA attack variants TSA-SQ and
>  TSA-L1
> X-Mailer: git-send-email 2.34.1
> 
> Transient Scheduler Attacks (TSA) are new speculative side channel attacks
> related to the execution timing of instructions under specific
> microarchitectural conditions. In some cases, an attacker may be able to
> use this timing information to infer data from other contexts, resulting in
> information leakage.
> 
> AMD has identified two sub-variants two variants of TSA.
> CPUID Fn8000_0021 ECX[1] (TSA_SQ_NO).
> 	If this bit is 1, the CPU is not vulnerable to TSA-SQ.
> 
> CPUID Fn8000_0021 ECX[2] (TSA_L1_NO).
> 	If this bit is 1, the CPU is not vulnerable to TSA-L1.
> 
> Add the new feature word FEAT_8000_0021_ECX and corresponding bits to
> detect TSA variants.
> 
> Link: https://www.amd.com/content/dam/amd/en/documents/resources/bulletin/technical-guidance-for-mitigating-transient-scheduler-attacks.pdf
> Co-developed-by: Borislav Petkov (AMD) <bp@alien8.de>
> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
> v2: Split the patches into two.
>     Not adding the feature bit in CPU model now. Users can add the feature
>     bits by using the option "-cpu EPYC-Genoa,+tsa-sq-no,+tsa-l1-no".
> 
> v1: https://lore.kernel.org/qemu-devel/20250709104956.GAaG5JVO-74EF96hHO@fat_crate.local/
> ---
>  target/i386/cpu.c | 17 +++++++++++++++++
>  target/i386/cpu.h |  6 ++++++
>  2 files changed, 23 insertions(+)

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>