All of lore.kernel.org
 help / color / mirror / Atom feed
From: Oliver Upton <oliver.upton@linux.dev>
To: Eric Auger <eauger@redhat.com>
Cc: kvmarm@lists.linux.dev, Marc Zyngier <maz@kernel.org>,
	Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Raghavendra Rao Ananta <rananta@google.com>,
	Zhou Wang <wangzhou1@hisilicon.com>
Subject: Re: [PATCH v4 6/6] Documentation: KVM: arm64: Describe VGICv3 registers writable pre-init
Date: Tue, 22 Jul 2025 14:50:21 -0700	[thread overview]
Message-ID: <aIAHnUZiSB3YGqoj@linux.dev> (raw)
In-Reply-To: <2fecf7c9-7eb2-4bda-bf4f-03b4a1a8f871@redhat.com>

On Mon, Jul 14, 2025 at 05:06:10PM +0200, Eric Auger wrote:
> Hi,
> 
> On 7/9/25 11:14 PM, Oliver Upton wrote:
> > KVM allows userspace to control GICD_IIDR.Revision and
> > GICD_TYPER2.nASSGIcap prior to initialization for the sake of
> > provisioning the guest-visible feature set. Document the userspace
> > expectations surrounding accesses to these registers.
> > 
> > Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
> > ---
> >  Documentation/virt/kvm/devices/arm-vgic-v3.rst | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> > 
> > diff --git a/Documentation/virt/kvm/devices/arm-vgic-v3.rst b/Documentation/virt/kvm/devices/arm-vgic-v3.rst
> > index e860498b1e35..c7a1cd22d814 100644
> > --- a/Documentation/virt/kvm/devices/arm-vgic-v3.rst
> > +++ b/Documentation/virt/kvm/devices/arm-vgic-v3.rst
> > @@ -78,6 +78,8 @@ Groups:
> >      -ENXIO   The group or attribute is unknown/unsupported for this device
> >               or hardware support is missing.
> >      -EFAULT  Invalid user pointer for attr->addr.
> > +    -EBUSY   Attempt to write a register that is read-only after
> > +             initialization
> >      =======  =============================================================
> >  
> >  
> > @@ -120,6 +122,15 @@ Groups:
> >      Note that distributor fields are not banked, but return the same value
> >      regardless of the mpidr used to access the register.
> >  
> > +    Userspace is allowed to write the following register fields prior to
> > +    initialization of the VGIC:
> > +
> > +      =====================
> > +      GICD_IIDR.Revision
> > +      GICD_TYPER2.nASSGIcap
> > +      =====================
> > +
> > +
> >      GICD_IIDR.Revision is updated when the KVM implementation is changed in a
> >      way directly observable by the guest or userspace.  Userspace should read
> >      GICD_IIDR from KVM and write back the read value to confirm its expected
> > @@ -128,6 +139,12 @@ Groups:
> >      behavior.
> >  
> >  
> > +    GICD_TYPER2.nASSGIcap allows userspace to control the support of SGIs
> > +    without an active state. At VGIC creation the field resets to the
> In [PATCH v4 4/6] KVM: arm64: vgic-v3: Allow userspace to write
> GICD_TYPER2.nASSGIcap commit message it was said:
> 
> "For convenience, bundle support for vLPIs and vSGIs behind this
> feature,allowing userspace to control vPE allocation for VMs in
> environments that may be constrained on vPE IDs."
> 
> which, I understand goes beyond the simple support of vSGIs. Maybe worth
> a clarification.

I would like to omit that language from the documentation. Giving
userspace the impression of controlling the host allocation is a bit odd
and nothing stops us from implementing nASSGIcap for software-injected
SGIs.

vPE allocation should be a non-issue for correctly provisioned
implementations.

Thanks,
Oliver

      reply	other threads:[~2025-07-22 21:50 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-09 21:14 [PATCH v4 0/6] KVM: arm64: Allow userspace to write GICD_TYPER2.nASSGIcap Oliver Upton
2025-07-09 21:14 ` [PATCH v4 1/6] KVM: arm64: Disambiguate support for vSGIs v. vLPIs Oliver Upton
2025-07-10  8:59   ` Ben Horgan
2025-07-10 16:22     ` Oliver Upton
2025-07-14 10:20   ` Eric Auger
2025-07-22 21:36     ` Oliver Upton
2025-07-09 21:14 ` [PATCH v4 2/6] KVM: arm64: vgic-v3: Consolidate MAINT_IRQ handling Oliver Upton
2025-07-14 12:52   ` Eric Auger
2025-07-14 12:59     ` Eric Auger
2025-07-22 21:42     ` Oliver Upton
2025-07-09 21:14 ` [PATCH v4 3/6] KVM: arm64: vgic-v3: Allow access to GICD_IIDR prior to initialization Oliver Upton
2025-07-14 14:41   ` Eric Auger
2025-07-22 21:47     ` Oliver Upton
2025-08-21 10:55   ` Zhou Wang
2025-08-21 18:43     ` Oliver Upton
2025-08-22  1:54       ` Zhou Wang
2025-07-09 21:14 ` [PATCH v4 4/6] KVM: arm64: vgic-v3: Allow userspace to write GICD_TYPER2.nASSGIcap Oliver Upton
2025-07-14 14:58   ` Eric Auger
2025-07-09 21:14 ` [PATCH v4 5/6] KVM: arm64: selftests: Add test for nASSGIcap attribute Oliver Upton
2025-07-14 15:03   ` Eric Auger
2025-07-09 21:14 ` [PATCH v4 6/6] Documentation: KVM: arm64: Describe VGICv3 registers writable pre-init Oliver Upton
2025-07-14 15:06   ` Eric Auger
2025-07-22 21:50     ` Oliver Upton [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=aIAHnUZiSB3YGqoj@linux.dev \
    --to=oliver.upton@linux.dev \
    --cc=eauger@redhat.com \
    --cc=joey.gouly@arm.com \
    --cc=kvmarm@lists.linux.dev \
    --cc=maz@kernel.org \
    --cc=rananta@google.com \
    --cc=suzuki.poulose@arm.com \
    --cc=wangzhou1@hisilicon.com \
    --cc=yuzenghui@huawei.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.