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Fri, 25 Jul 2025 07:20:29 -0700 (PDT) Date: Fri, 25 Jul 2025 07:20:26 -0700 From: Deepak Gupta To: Heinrich Schuchardt Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kbuild@vger.kernel.org, linux-mm@kvack.org, llvm@lists.linux.dev, rick.p.edgecombe@intel.com, broonie@kernel.org, cleger@rivosinc.com, samitolvanen@google.com, apatel@ventanamicro.com, ajones@ventanamicro.com, conor.dooley@microchip.com, charlie@rivosinc.com, samuel.holland@sifive.com, bjorn@rivosinc.com, fweimer@redhat.com, jeffreyalaw@gmail.com, andrew@sifive.com, ved@rivosinc.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Masahiro Yamada , Nathan Chancellor , Nicolas Schier , Andrew Morton , David Hildenbrand , Lorenzo Stoakes , "Liam R. Howlett" , Vlastimil Babka , Mike Rapoport , Suren Baghdasaryan , Michal Hocko , Nick Desaulniers , Bill Wendling , Monk Chiang , Kito Cheng , Justin Stitt Subject: Re: [PATCH 05/11] riscv: enable landing pad enforcement Message-ID: References: <20250724-riscv_kcfi-v1-0-04b8fa44c98c@rivosinc.com> <20250724-riscv_kcfi-v1-5-04b8fa44c98c@rivosinc.com> <1149732f-bc8d-4339-90c3-e34aeac9f1be@canonical.com> Precedence: bulk X-Mailing-List: linux-kbuild@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <1149732f-bc8d-4339-90c3-e34aeac9f1be@canonical.com> On Fri, Jul 25, 2025 at 08:33:46AM +0200, Heinrich Schuchardt wrote: >On 25.07.25 01:36, Deepak Gupta wrote: >>Enables landing pad enforcement by invoking a SBI FWFT call. >> >>Signed-off-by: Deepak Gupta >>--- >> arch/riscv/kernel/asm-offsets.c | 1 + >> arch/riscv/kernel/head.S | 19 +++++++++++++++++++ >> 2 files changed, 20 insertions(+) >> >>diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c >>index e4d55126dc3e..e6a9fad86fae 100644 >>--- a/arch/riscv/kernel/asm-offsets.c >>+++ b/arch/riscv/kernel/asm-offsets.c >>@@ -536,6 +536,7 @@ void asm_offsets(void) >> DEFINE(SBI_EXT_FWFT, SBI_EXT_FWFT); >> DEFINE(SBI_EXT_FWFT_SET, SBI_EXT_FWFT_SET); >> DEFINE(SBI_FWFT_SHADOW_STACK, SBI_FWFT_SHADOW_STACK); >>+ DEFINE(SBI_FWFT_LANDING_PAD, SBI_FWFT_LANDING_PAD); >> DEFINE(SBI_FWFT_SET_FLAG_LOCK, SBI_FWFT_SET_FLAG_LOCK); >> #endif >> } >>diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S >>index 9c99c5ad6fe8..59af044bf85c 100644 >>--- a/arch/riscv/kernel/head.S >>+++ b/arch/riscv/kernel/head.S >>@@ -185,6 +185,16 @@ secondary_start_sbi: >> 1: >> #endif >> scs_load_current >>+ >>+#if defined(CONFIG_RISCV_SBI) && defined(CONFIG_RISCV_KERNEL_CFI) >>+ li a7, SBI_EXT_FWFT >>+ li a6, SBI_EXT_FWFT_SET >>+ li a0, SBI_FWFT_LANDING_PAD >>+ li a1, 1 /* enable landing pad for supervisor */ >>+ li a2, SBI_FWFT_SET_FLAG_LOCK >>+ ecall /* check for error condition and take appropriate action */ >>+#endif >>+ >> call smp_callin >> #endif /* CONFIG_SMP */ >>@@ -359,6 +369,15 @@ SYM_CODE_START(_start_kernel) >> #endif >> scs_load_current >>+#if defined(CONFIG_RISCV_SBI) && defined(CONFIG_RISCV_KERNEL_CFI) >>+ li a7, SBI_EXT_FWFT >>+ li a6, SBI_EXT_FWFT_SET >>+ li a0, SBI_FWFT_LANDING_PAD >>+ li a1, 1 /* enable landing pad for supervisor */ > >The SBI specification calls BIT(0) "LOCK". >Shouldn't we define a constant for the lock bit instead of using a >magic value? See below `li a2, SBI_FWFT_SET_FLAG_LOCK`. "li a1, 1 /* enable landing pad for supervisor */>" --> this is enabling. Had we done "li a1, 0 /* enable landing pad for supervisor */" --> this is asking firmware to disable the feature (turn off the bit in menvcfg CSR) >Best regards > >Heinrich > >>+ li a2, SBI_FWFT_SET_FLAG_LOCK >>+ ecall /* check for error condition and take appropriate action */ >>+#endif >>+ >> #ifdef CONFIG_KASAN >> call kasan_early_init >> #endif >> > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CEB76C87FCE for ; Fri, 25 Jul 2025 14:20:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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Fri, 25 Jul 2025 07:20:30 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-31e60a61628sm2176473a91.1.2025.07.25.07.20.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Jul 2025 07:20:29 -0700 (PDT) Date: Fri, 25 Jul 2025 07:20:26 -0700 From: Deepak Gupta To: Heinrich Schuchardt Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kbuild@vger.kernel.org, linux-mm@kvack.org, llvm@lists.linux.dev, rick.p.edgecombe@intel.com, broonie@kernel.org, cleger@rivosinc.com, samitolvanen@google.com, apatel@ventanamicro.com, ajones@ventanamicro.com, conor.dooley@microchip.com, charlie@rivosinc.com, samuel.holland@sifive.com, bjorn@rivosinc.com, fweimer@redhat.com, jeffreyalaw@gmail.com, andrew@sifive.com, ved@rivosinc.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Masahiro Yamada , Nathan Chancellor , Nicolas Schier , Andrew Morton , David Hildenbrand , Lorenzo Stoakes , "Liam R. Howlett" , Vlastimil Babka , Mike Rapoport , Suren Baghdasaryan , Michal Hocko , Nick Desaulniers , Bill Wendling , Monk Chiang , Kito Cheng , Justin Stitt Subject: Re: [PATCH 05/11] riscv: enable landing pad enforcement Message-ID: References: <20250724-riscv_kcfi-v1-0-04b8fa44c98c@rivosinc.com> <20250724-riscv_kcfi-v1-5-04b8fa44c98c@rivosinc.com> <1149732f-bc8d-4339-90c3-e34aeac9f1be@canonical.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1149732f-bc8d-4339-90c3-e34aeac9f1be@canonical.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250725_072030_978072_F3A2440A X-CRM114-Status: GOOD ( 10.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Jul 25, 2025 at 08:33:46AM +0200, Heinrich Schuchardt wrote: >On 25.07.25 01:36, Deepak Gupta wrote: >>Enables landing pad enforcement by invoking a SBI FWFT call. >> >>Signed-off-by: Deepak Gupta >>--- >> arch/riscv/kernel/asm-offsets.c | 1 + >> arch/riscv/kernel/head.S | 19 +++++++++++++++++++ >> 2 files changed, 20 insertions(+) >> >>diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c >>index e4d55126dc3e..e6a9fad86fae 100644 >>--- a/arch/riscv/kernel/asm-offsets.c >>+++ b/arch/riscv/kernel/asm-offsets.c >>@@ -536,6 +536,7 @@ void asm_offsets(void) >> DEFINE(SBI_EXT_FWFT, SBI_EXT_FWFT); >> DEFINE(SBI_EXT_FWFT_SET, SBI_EXT_FWFT_SET); >> DEFINE(SBI_FWFT_SHADOW_STACK, SBI_FWFT_SHADOW_STACK); >>+ DEFINE(SBI_FWFT_LANDING_PAD, SBI_FWFT_LANDING_PAD); >> DEFINE(SBI_FWFT_SET_FLAG_LOCK, SBI_FWFT_SET_FLAG_LOCK); >> #endif >> } >>diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S >>index 9c99c5ad6fe8..59af044bf85c 100644 >>--- a/arch/riscv/kernel/head.S >>+++ b/arch/riscv/kernel/head.S >>@@ -185,6 +185,16 @@ secondary_start_sbi: >> 1: >> #endif >> scs_load_current >>+ >>+#if defined(CONFIG_RISCV_SBI) && defined(CONFIG_RISCV_KERNEL_CFI) >>+ li a7, SBI_EXT_FWFT >>+ li a6, SBI_EXT_FWFT_SET >>+ li a0, SBI_FWFT_LANDING_PAD >>+ li a1, 1 /* enable landing pad for supervisor */ >>+ li a2, SBI_FWFT_SET_FLAG_LOCK >>+ ecall /* check for error condition and take appropriate action */ >>+#endif >>+ >> call smp_callin >> #endif /* CONFIG_SMP */ >>@@ -359,6 +369,15 @@ SYM_CODE_START(_start_kernel) >> #endif >> scs_load_current >>+#if defined(CONFIG_RISCV_SBI) && defined(CONFIG_RISCV_KERNEL_CFI) >>+ li a7, SBI_EXT_FWFT >>+ li a6, SBI_EXT_FWFT_SET >>+ li a0, SBI_FWFT_LANDING_PAD >>+ li a1, 1 /* enable landing pad for supervisor */ > >The SBI specification calls BIT(0) "LOCK". >Shouldn't we define a constant for the lock bit instead of using a >magic value? See below `li a2, SBI_FWFT_SET_FLAG_LOCK`. "li a1, 1 /* enable landing pad for supervisor */>" --> this is enabling. Had we done "li a1, 0 /* enable landing pad for supervisor */" --> this is asking firmware to disable the feature (turn off the bit in menvcfg CSR) >Best regards > >Heinrich > >>+ li a2, SBI_FWFT_SET_FLAG_LOCK >>+ ecall /* check for error condition and take appropriate action */ >>+#endif >>+ >> #ifdef CONFIG_KASAN >> call kasan_early_init >> #endif >> > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv