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Fri, 25 Jul 2025 14:04:31 -0700 (PDT) Received: from localhost ([2a00:79e0:2e14:7:5a7:d366:b2e1:fcd1]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-7640b2ddbbdsm373592b3a.104.2025.07.25.14.04.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Jul 2025 14:04:30 -0700 (PDT) Date: Fri, 25 Jul 2025 14:04:28 -0700 From: Brian Norris To: Manivannan Sadhasivam Cc: Bartosz Golaszewski , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Krishna Chaitanya Chundru Subject: Re: [PATCH RFC 2/3] PCI/pwrctrl: Allow pwrctrl core to control PERST# GPIO if available Message-ID: References: <20250707-pci-pwrctrl-perst-v1-0-c3c7e513e312@kernel.org> <20250707-pci-pwrctrl-perst-v1-2-c3c7e513e312@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Thanks for clearing up some confusion. I was misled on some aspects. But I think there's still a problem in here: On Thu, Jul 24, 2025 at 07:43:38PM +0530, Manivannan Sadhasivam wrote: > On Sat, Jul 12, 2025 at 01:59:34PM GMT, Manivannan Sadhasivam wrote: > > On Fri, Jul 11, 2025 at 05:38:16PM GMT, Brian Norris wrote: > > > On Mon, Jul 07, 2025 at 11:48:39PM +0530, Manivannan Sadhasivam wrote: > > > > PERST# is an (optional) auxiliary signal provided by the PCIe host to > > > > components for signalling 'Fundamental Reset' as per the PCIe spec r6.0, > > > > sec 6.6.1. > > > > > > > void pci_pwrctrl_init(struct pci_pwrctrl *pwrctrl, struct device *dev) > > > > { > > > > + struct pci_host_bridge *host_bridge = to_pci_host_bridge(dev->parent); > > > > + int devfn; > > > > + > > > > pwrctrl->dev = dev; > > > > INIT_WORK(&pwrctrl->work, rescan_work_func); > > > > + > > > > + if (!host_bridge->perst) > > > > + return; > > > > + > > > > + devfn = of_pci_get_devfn(dev_of_node(dev)); > > > > + if (devfn >= 0 && host_bridge->perst[PCI_SLOT(devfn)]) > > > > > > This seems to imply a 1:1 correlation between slots and pwrctrl devices, > > > almost as if you expect everyone is using drivers/pci/pwrctrl/slot.c. > > > But there is also endpoint-specific pwrctrl support, and there's quite > > > a bit of flexibility around what these hierarchies can look like. > > > > > > How do you account for that? > > > > > > For example, couldn't you have both a "port" and an "endpoint" pwrctrl? Would > > > they both grab the same PERST# GPIO here? And might that incur excessive > > > resets, possibly even clobbering each other? ... > I realized that there is no need to define these properties (PERST#, WAKE#, > CLKREQ#) in the endpoint node (the DT binding also doesn't allow now anyway). > These properties should just exist in the Root Port node as there can be only > one set per hierarchy i.e., Root Complex would only use one set of these GPIOs > per Root Port and the endpoint need to share them. That implies it's not a 1:1 correlation between PERST# GPIO and pwrctrl device. Multiple endpoints might need powered up, but they may share a PERST#. I don't think this patch solves this properly, as it allows the first one to deassert PERST# before the other(s) are powered. Or maybe I'm missing something yet again :) Brian