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[34.87.131.208]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76bd9b3b3d4sm32813235b3a.10.2025.08.14.06.34.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Aug 2025 06:34:14 -0700 (PDT) Date: Thu, 14 Aug 2025 13:34:09 +0000 From: Pranjal Shrivastava To: kernel test robot Cc: Nicolin Chen , oe-kbuild-all@lists.linux.dev, linux-kernel@vger.kernel.org, Jason Gunthorpe , Alok Tiwari Subject: Re: drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c:305:47: sparse: sparse: incorrect type in assignment (different base types) Message-ID: References: <202508142105.Jb5Smjsg-lkp@intel.com> Precedence: bulk X-Mailing-List: oe-kbuild-all@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <202508142105.Jb5Smjsg-lkp@intel.com> On Thu, Aug 14, 2025 at 09:21:50PM +0800, kernel test robot wrote: > tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master > head: 0cc53520e68bea7fb80fdc6bdf8d226d1b6a98d9 > commit: 32b2d3a57e26804ca96d82a222667ac0fa226cb7 iommu/tegra241-cmdqv: Add IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV support > date: 5 weeks ago > config: arm64-randconfig-r112-20250814 (https://download.01.org/0day-ci/archive/20250814/202508142105.Jb5Smjsg-lkp@intel.com/config) > compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 3769ce013be2879bf0b329c14a16f5cb766f26ce) > reproduce: (https://download.01.org/0day-ci/archive/20250814/202508142105.Jb5Smjsg-lkp@intel.com/reproduce) > > If you fix the issue in a separate patch/commit (i.e. not just a new version of > the same patch/commit), kindly add following tags > | Reported-by: kernel test robot > | Closes: https://lore.kernel.org/oe-kbuild-all/202508142105.Jb5Smjsg-lkp@intel.com/ > > sparse warnings: (new ones prefixed by >>) > >> drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c:305:47: sparse: sparse: incorrect type in assignment (different base types) @@ expected restricted __le64 @@ got unsigned long long @@ > drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c:305:47: sparse: expected restricted __le64 > drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c:305:47: sparse: got unsigned long long > > vim +305 drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c > > 297 > 298 static void tegra241_vintf_user_handle_error(struct tegra241_vintf *vintf) > 299 { > 300 struct iommufd_viommu *viommu = &vintf->vsmmu.core; > 301 struct iommu_vevent_tegra241_cmdqv vevent_data; > 302 int i; > 303 > 304 for (i = 0; i < LVCMDQ_ERR_MAP_NUM_64; i++) > > 305 vevent_data.lvcmdq_err_map[i] = > 306 readq_relaxed(REG_VINTF(vintf, LVCMDQ_ERR_MAP_64(i))); > 307 > 308 iommufd_viommu_report_event(viommu, IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, > 309 &vevent_data, sizeof(vevent_data)); > 310 } > 311 > I assume we'd need something like the following (untested) for this: --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c @@ -303,8 +303,8 @@ for (i = 0; i < LVCMDQ_ERR_MAP_NUM_64; i++) vevent_data.lvcmdq_err_map[i] = - readq_relaxed(REG_VINTF(vintf, LVCMDQ_ERR_MAP_64(i))); + cpu_to_le64(readq_relaxed(REG_VINTF(vintf, LVCMDQ_ERR_MAP_64(i)))); iommufd_viommu_report_event(viommu, IOMMU_VEVENTQ_TYPE_TEGRA241_CMDQV, &vevent_data, sizeof(vevent_data)); > -- > 0-DAY CI Kernel Test Service > https://github.com/intel/lkp-tests/wiki