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Peter Anvin" , Andy Lutomirski , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Paolo Bonzini , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, loongarch@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Kan Liang , Yongwei Ma , Mingwei Zhang , Xiong Zhang , Sandipan Das , Dapeng Mi X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250815_085528_098468_18562894 X-CRM114-Status: GOOD ( 18.48 ) X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+kvm-riscv=archiver.kernel.org@lists.infradead.org On Fri, Aug 15, 2025, Sean Christopherson wrote: > On Fri, Aug 15, 2025, Peter Zijlstra wrote: > > > diff --git a/kernel/events/core.c b/kernel/events/core.c > > > index e1df3c3bfc0d..ad22b182762e 100644 > > > --- a/kernel/events/core.c > > > +++ b/kernel/events/core.c > > > @@ -6408,6 +6408,8 @@ void perf_load_guest_context(unsigned long data) > > > task_ctx_sched_out(cpuctx->task_ctx, NULL, EVENT_GUEST); > > > } > > > > > > + arch_perf_load_guest_context(data); > > > > So I still don't understand why this ever needs to reach the generic > > code. x86 pmu driver and x86 kvm can surely sort this out inside of x86, > > no? > > It's definitely possible to handle this entirely within x86, I just don't love > switching the LVTPC without the protection of perf_ctx_lock and perf_ctx_disable(). > It's not a sticking point for me if you strongly prefer something like this: > > diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c > index 0e5048ae86fa..86b81c217b97 100644 > --- a/arch/x86/kvm/pmu.c > +++ b/arch/x86/kvm/pmu.c > @@ -1319,7 +1319,9 @@ void kvm_mediated_pmu_load(struct kvm_vcpu *vcpu) > > lockdep_assert_irqs_disabled(); > > - perf_load_guest_context(kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVTPC)); > + perf_load_guest_context(); > + > + perf_load_guest_lvtpc(kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVTPC)); Hmm, an argument for providing a dedicated perf_load_guest_lvtpc() APIs is that it would allow KVM to handle LVTPC writes in KVM's VM-Exit fastpath, i.e. without having to do a full put+reload of the guest context. So if we're confident that switching the host LVTPC outside of perf_{load,put}_guest_context() is functionally safe, I'm a-ok with it. > /* > * Disable all counters before loading event selectors and PMCs so that > @@ -1380,5 +1382,7 @@ void kvm_mediated_pmu_put(struct kvm_vcpu *vcpu) > > kvm_pmu_put_guest_pmcs(vcpu); > > + perf_put_guest_lvtpc(); > + > perf_put_guest_context(); > } > -- kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D816308F10 for ; Fri, 15 Aug 2025 15:55:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755273328; cv=none; b=GIuQ35FXW7N/3aLv4vU7mUr+jilt+L65kOo9RLixq4onntaSKuMrCaKSUb2pD1SfT+BDQ85u1WOY+ncdF0vuhJQ5gTnGHMX9K/nEncoCijFRDqaToDz4Z3IGeD9a0XPVpzQcnnOclb6EWwoTuNg2Vy569CCbl0yOXoYx6DDIE+A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755273328; c=relaxed/simple; bh=wGA20jXRveGy5A3RdSltG8Mhq+1vci/NEVKX+vkU7E8=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=Kl7dQ6JVqn7DhK9ZjfXYQlNc6QDABG04Sckix8cIYLBF6rzth+sU5/7437vY0c0HdL+db5e7tUsvT2Kohy480Rh/cUnTmWQflD7/82920VwjBSIHdF9/Oo2ZtGU8n3oaNkei0tSXSCBDYYZIXcXe21fzS7BU1XHoSulBZigWLhw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=x3oYtxMa; arc=none smtp.client-ip=209.85.215.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="x3oYtxMa" Received: by mail-pg1-f201.google.com with SMTP id 41be03b00d2f7-b4716fb7f2aso1478556a12.0 for ; Fri, 15 Aug 2025 08:55:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1755273327; x=1755878127; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=z7Sa/kyYZ4LkgwyCX9rJEJ7u8HAAn0SslzIHQ/FhmRM=; b=x3oYtxMaycpQa+ZiFdutQkYdge2OTwH6KHNjeAXf7z48MhvczOS6w7AZRYD71S2rIX o00TZfrvCIHMcRe6fxP1zBLFeT3jY/DPHV7OCD0ZOKveJnmMqJ166nqKOMAKAtDOm10J RFQnqOETLIJPtCxNK1XXlQEQDireX42B/nYkEMgAkJ6zDz7em7l1lFSrH3l2bQtHvsh7 pUFIaYWdGCIvTEx/vM0NZITlN00HB3nAueFVvWWtFB0r4bTn4AY1DspH8rbs9BxoFYjH iilCdbjPjxgPTF/bocZ259O8Q4KpRTPq+hY4/1vK9KqTjDh7ZS4EoNQAMLy0kYV1bgF5 QUuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755273327; x=1755878127; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=z7Sa/kyYZ4LkgwyCX9rJEJ7u8HAAn0SslzIHQ/FhmRM=; b=HmUzubsHnmYd1dHCYU/1GTia4TADhG6O4ELOahTGNOH+048Dml5pyyPtJse89lJ6Rh 88segjLmZR/Fqq1BzIwSEXz/bSxvadUKRbCHViV8mRLf5FLTSZN9gtP3jO6ybaohhbfy 18iW2gquRvUlLQehrf0raRfKp8QlNpH32I0LFPDa6t3+W1sTy6utFfFajhUMtfXS20gV nBJ1zuhYdA3N8vo70Tq3DfR/FA2G6+SMGkGmmCosZx3ADmk0Ih+FbdC++haNFIlLK9x2 X616Wx5/1/2s5v3Qv7DXpa+JYR630qu9sORiu2KJV3vPw/dTvwzfdwNeLnP2qAcKGffc iAsA== X-Forwarded-Encrypted: i=1; AJvYcCU76+Yyv7kXJYRGiZyg8FosEQN6fVdOyHYExXugWJr6CSM6AaWXPXCs/sMd9Yyz0S1ImRc=@vger.kernel.org X-Gm-Message-State: AOJu0YyFoV7NDuY3YI680MI9B6ti6/ykQxtMzk8ta4UaKK4xXouawW8V u58n2Vq/w7t2HZijfg8kFIQmINu8H9PnIF463YqVPeCyrJ9H7RJegs1zvaj4GVUPzpDwd95YuEr F01iFJQ== X-Google-Smtp-Source: AGHT+IEdU+o+jxQRQjpxYUV2M2swV17WB5j94o9nqbjzzuHzapwMPWAh/lqVZpiY/Ko0sm3v0aaj/KNyHyA= X-Received: from pjbpl10.prod.google.com ([2002:a17:90b:268a:b0:321:370d:cae5]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90a:ec86:b0:313:dcf4:37bc with SMTP id 98e67ed59e1d1-323421229eamr3334693a91.34.1755273326710; Fri, 15 Aug 2025 08:55:26 -0700 (PDT) Date: Fri, 15 Aug 2025 08:55:25 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250806195706.1650976-1-seanjc@google.com> <20250806195706.1650976-10-seanjc@google.com> <20250815113951.GC4067720@noisy.programming.kicks-ass.net> Message-ID: Subject: Re: [PATCH v5 09/44] perf/x86: Switch LVTPC to/from mediated PMI vector on guest load/put context From: Sean Christopherson To: Peter Zijlstra Cc: Marc Zyngier , Oliver Upton , Tianrui Zhao , Bibo Mao , Huacai Chen , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Xin Li , "H. Peter Anvin" , Andy Lutomirski , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Paolo Bonzini , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, loongarch@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Kan Liang , Yongwei Ma , Mingwei Zhang , Xiong Zhang , Sandipan Das , Dapeng Mi Content-Type: text/plain; charset="us-ascii" On Fri, Aug 15, 2025, Sean Christopherson wrote: > On Fri, Aug 15, 2025, Peter Zijlstra wrote: > > > diff --git a/kernel/events/core.c b/kernel/events/core.c > > > index e1df3c3bfc0d..ad22b182762e 100644 > > > --- a/kernel/events/core.c > > > +++ b/kernel/events/core.c > > > @@ -6408,6 +6408,8 @@ void perf_load_guest_context(unsigned long data) > > > task_ctx_sched_out(cpuctx->task_ctx, NULL, EVENT_GUEST); > > > } > > > > > > + arch_perf_load_guest_context(data); > > > > So I still don't understand why this ever needs to reach the generic > > code. x86 pmu driver and x86 kvm can surely sort this out inside of x86, > > no? > > It's definitely possible to handle this entirely within x86, I just don't love > switching the LVTPC without the protection of perf_ctx_lock and perf_ctx_disable(). > It's not a sticking point for me if you strongly prefer something like this: > > diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c > index 0e5048ae86fa..86b81c217b97 100644 > --- a/arch/x86/kvm/pmu.c > +++ b/arch/x86/kvm/pmu.c > @@ -1319,7 +1319,9 @@ void kvm_mediated_pmu_load(struct kvm_vcpu *vcpu) > > lockdep_assert_irqs_disabled(); > > - perf_load_guest_context(kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVTPC)); > + perf_load_guest_context(); > + > + perf_load_guest_lvtpc(kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVTPC)); Hmm, an argument for providing a dedicated perf_load_guest_lvtpc() APIs is that it would allow KVM to handle LVTPC writes in KVM's VM-Exit fastpath, i.e. without having to do a full put+reload of the guest context. So if we're confident that switching the host LVTPC outside of perf_{load,put}_guest_context() is functionally safe, I'm a-ok with it. > /* > * Disable all counters before loading event selectors and PMCs so that > @@ -1380,5 +1382,7 @@ void kvm_mediated_pmu_put(struct kvm_vcpu *vcpu) > > kvm_pmu_put_guest_pmcs(vcpu); > > + perf_put_guest_lvtpc(); > + > perf_put_guest_context(); > } > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E756CA0EE4 for ; Fri, 15 Aug 2025 17:33:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=6hfitMd8cccN+p7TFrGeSGQe67qXl4IC5D7i0h0fLN4=; b=jG/3wdRfeKvUY3qKy8ClJaeUA2 BZjtfekrokgxgeMC06VPWbm975LGMgsUANs0lXZPN5uxNH/sh1SfKQrM39PR4fTjx+G6UE5Gb3n0E BHY19qnZhut8oQiJJIxkO8O1Khd/qMbT7WIbMvqcTpZZ0qoQfCfvAO4Pt1Qceeigd8gYPUnEviiXU 9J2S20fmSC+Loqiw3/uWjRh7kmJuKoXq82b9iImVDFx/Tq9pQQzM+WCAzG7S8FSsbVfBea0bbiwYB BWr4bHG/rGWDqK/bYQP8IMsxAJrCJ86aQ/9aL2huWfQpuc1E0b1yRC6K5cUTznsrgPeL+RGnD6uba sreMnUzw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1umyIT-000000038Em-2UNd; Fri, 15 Aug 2025 17:32:57 +0000 Received: from mail-pj1-x1049.google.com ([2607:f8b0:4864:20::1049]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1umwm8-00000002tVo-0ylZ for linux-riscv@lists.infradead.org; Fri, 15 Aug 2025 15:55:29 +0000 Received: by mail-pj1-x1049.google.com with SMTP id 98e67ed59e1d1-323267858edso2178142a91.1 for ; Fri, 15 Aug 2025 08:55:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1755273327; x=1755878127; darn=lists.infradead.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=z7Sa/kyYZ4LkgwyCX9rJEJ7u8HAAn0SslzIHQ/FhmRM=; b=NxJZej/HLtDeAecvavdWhH6jnbB6EeJIGW8/pUipCwZEI2kNfjpGC9WfanJxTn4C/X jFGWSuGJ/sGR51//diLFvJoGDuuxCxcvUCnxh1UDvtxrVniv261AVm7rHVUI8S0LbjA7 0YMNS54b/+dhFRWRf0uRIOYXEZXVcAQ6ykk7SiOQPWodDgY3etveT/5tGgEwdsqOQlNd mbZnfu2X+miZZq4qqF69S0mPaOeOTZy3EpgO4mU/p1C0MJix1sfL3UgqDt1jlvPcsw81 1ijR+bJ/JSiJJeLvf3jqBAtJq8EUPHObiPiDURNzPQqCUfcwRTjsrzE7Dj7ovjO9PCyC oyfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755273327; x=1755878127; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=z7Sa/kyYZ4LkgwyCX9rJEJ7u8HAAn0SslzIHQ/FhmRM=; b=n1E8EZQWhFtFq+4LSErAhcmQ9PW9DTRSiFagPHZqgzcj6YtRoS6oWvz6u/tPnQOE9X ktHbv8/AIeSvlJbLHBzIePJxyC7BBxJtzOG+OwN/6IPCSfRYF/rfQejtqXs+DYHfD20Q eOmt3gqnPCVtGAp7QrSlPnbtFPcvwG8Xt6GA9gOqGAHe0Ohat0NEAi8z1Kxo41zVr8Er ACneaanJTo2XxnWAT84uF7jDNMIH/FOXESytt56fIJjNSvJRiUcfRaV0qsdPIBQprKPb LO6g/EaO84IoGIRd22+n4XEGaisgMHMyxOlD+9g/BbcXonwOt4RnD58tGPKwQV9ElkTz 8u/w== X-Forwarded-Encrypted: i=1; AJvYcCWj0JWR5qpi8yjFZcsNismDZF333WMA6LkXK0mTEXLCXqFVDxZbbR6DsVC933/b+hFuSq4R8M2sUBKiTQ==@lists.infradead.org X-Gm-Message-State: AOJu0YyivpBQpbF+JFYSmlFyGUw8I+2RWxLY6sy0ht+CYM4qGvg1lJmQ sPSAKQxr1fjVdtUbyDMbWQe3aSq64eyfw3r9j9coTJnS1l6aqpiOdZfuBeGTo2WN49midLw2MJM jfm0LjA== X-Google-Smtp-Source: AGHT+IEdU+o+jxQRQjpxYUV2M2swV17WB5j94o9nqbjzzuHzapwMPWAh/lqVZpiY/Ko0sm3v0aaj/KNyHyA= X-Received: from pjbpl10.prod.google.com ([2002:a17:90b:268a:b0:321:370d:cae5]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90a:ec86:b0:313:dcf4:37bc with SMTP id 98e67ed59e1d1-323421229eamr3334693a91.34.1755273326710; Fri, 15 Aug 2025 08:55:26 -0700 (PDT) Date: Fri, 15 Aug 2025 08:55:25 -0700 In-Reply-To: Mime-Version: 1.0 References: <20250806195706.1650976-1-seanjc@google.com> <20250806195706.1650976-10-seanjc@google.com> <20250815113951.GC4067720@noisy.programming.kicks-ass.net> Message-ID: Subject: Re: [PATCH v5 09/44] perf/x86: Switch LVTPC to/from mediated PMI vector on guest load/put context From: Sean Christopherson To: Peter Zijlstra Cc: Marc Zyngier , Oliver Upton , Tianrui Zhao , Bibo Mao , Huacai Chen , Anup Patel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Xin Li , "H. Peter Anvin" , Andy Lutomirski , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Paolo Bonzini , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, loongarch@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Kan Liang , Yongwei Ma , Mingwei Zhang , Xiong Zhang , Sandipan Das , Dapeng Mi X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250815_085528_278145_029556BB X-CRM114-Status: GOOD ( 18.48 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Aug 15, 2025, Sean Christopherson wrote: > On Fri, Aug 15, 2025, Peter Zijlstra wrote: > > > diff --git a/kernel/events/core.c b/kernel/events/core.c > > > index e1df3c3bfc0d..ad22b182762e 100644 > > > --- a/kernel/events/core.c > > > +++ b/kernel/events/core.c > > > @@ -6408,6 +6408,8 @@ void perf_load_guest_context(unsigned long data) > > > task_ctx_sched_out(cpuctx->task_ctx, NULL, EVENT_GUEST); > > > } > > > > > > + arch_perf_load_guest_context(data); > > > > So I still don't understand why this ever needs to reach the generic > > code. x86 pmu driver and x86 kvm can surely sort this out inside of x86, > > no? > > It's definitely possible to handle this entirely within x86, I just don't love > switching the LVTPC without the protection of perf_ctx_lock and perf_ctx_disable(). > It's not a sticking point for me if you strongly prefer something like this: > > diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c > index 0e5048ae86fa..86b81c217b97 100644 > --- a/arch/x86/kvm/pmu.c > +++ b/arch/x86/kvm/pmu.c > @@ -1319,7 +1319,9 @@ void kvm_mediated_pmu_load(struct kvm_vcpu *vcpu) > > lockdep_assert_irqs_disabled(); > > - perf_load_guest_context(kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVTPC)); > + perf_load_guest_context(); > + > + perf_load_guest_lvtpc(kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVTPC)); Hmm, an argument for providing a dedicated perf_load_guest_lvtpc() APIs is that it would allow KVM to handle LVTPC writes in KVM's VM-Exit fastpath, i.e. without having to do a full put+reload of the guest context. So if we're confident that switching the host LVTPC outside of perf_{load,put}_guest_context() is functionally safe, I'm a-ok with it. > /* > * Disable all counters before loading event selectors and PMCs so that > @@ -1380,5 +1382,7 @@ void kvm_mediated_pmu_put(struct kvm_vcpu *vcpu) > > kvm_pmu_put_guest_pmcs(vcpu); > > + perf_put_guest_lvtpc(); > + > perf_put_guest_context(); > } > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv