Re: [PATCH v3 6/8] clk: loongson2: Add clock definitions for Loongson 2K0300 SoC

[Yao Zi <ziyao@disroot.org>]

On Thu, Aug 07, 2025 at 07:21:32PM +0800, Huacai Chen wrote:
> Hi, Yao,
> 
> On Tue, Aug 5, 2025 at 11:05 PM Yao Zi <ziyao@disroot.org> wrote:
> >
> > The clock controller of Loongson 2K0300 consists of three PLLs, requires
> > an 120MHz external reference clock to function, and generates clocks in
> > various frequencies for SoC peripherals.
> >
> > Clock definitions for previous SoC generations could be reused for most
> > clock hardwares. There're two gates marked as critical, clk_node_gate
> > and clk_boot_gate, which supply the CPU cores and the system
> > configuration bus. Disabling them leads to a SoC hang.
> >
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> >  drivers/clk/clk-loongson2.c | 48 +++++++++++++++++++++++++++++++++++++
> >  1 file changed, 48 insertions(+)
> >
> > diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c
> > index 52a9f1c2794a..1d210a7683ea 100644
> > --- a/drivers/clk/clk-loongson2.c
> > +++ b/drivers/clk/clk-loongson2.c
> > @@ -12,6 +12,7 @@
> >  #include <linux/platform_device.h>
> >  #include <linux/io-64-nonatomic-lo-hi.h>
> >  #include <dt-bindings/clock/loongson,ls2k-clk.h>
> > +#include <dt-bindings/clock/loongson,ls2k0300-clk.h>
> >
> >  enum loongson2_clk_type {
> >         CLK_TYPE_PLL,
> > @@ -137,6 +138,52 @@ struct loongson2_clk_board_info {
> >                 .fixed_rate     = _rate,                        \
> >         }
> >
> > +static const struct loongson2_clk_board_info ls2k0300_clks[] = {
> > +       /* Reference Clock */
> > +       CLK_PLL(LS2K0300_PLL_NODE, "pll_node",   0x00, 15, 9, 8, 7),
> > +       CLK_PLL(LS2K0300_PLL_DDR,  "pll_ddr",    0x08, 15, 9, 8, 7),
> > +       CLK_PLL(LS2K0300_PLL_PIX,  "pll_pix",    0x10, 15, 9, 8, 7),
> > +       CLK_FIXED(LS2K0300_CLK_STABLE, "clk_stable", NULL, 100000000),
> > +       CLK_FIXED(LS2K0300_CLK_THSENS, "clk_thsens", NULL, 10000000),
> > +       /* Node PLL */
> > +       CLK_DIV(LS2K0300_CLK_NODE_DIV, "clk_node_div", "pll_node", 0x00, 24, 7),
> > +       CLK_DIV(LS2K0300_CLK_GMAC_DIV, "clk_gmac_div", "pll_node", 0x04, 0, 7),
> > +       CLK_DIV(LS2K0300_CLK_I2S_DIV,  "clk_i2s_div",  "pll_node", 0x04, 8, 7),
> > +       CLK_GATE(LS2K0300_CLK_NODE_PLL_GATE,   "clk_node_pll_gate", "clk_node_div", 0x00, 0),
> > +       CLK_GATE(LS2K0300_CLK_GMAC_GATE,       "clk_gmac_gate",     "clk_gmac_div", 0x00, 1),
> > +       CLK_GATE(LS2K0300_CLK_I2S_GATE,        "clk_i2s_gate",      "clk_i2s_div", 0x00, 2),
> > +       CLK_GATE_FLAGS(LS2K0300_CLK_NODE_GATE, "clk_node_gate",     "clk_node_scale",
> > +                      0x24, 0, CLK_IS_CRITICAL),
> There is no 80 chars limit now, so feel free to define a clock in one line.

Thanks, will merge definitions into a single line in the next version.

Best regards,
Yao Zi