From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Cc: linux-renesas-soc@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: Re: [PATCH 3/4] arm64: dts: renesas: rzg3s-smarc-som: Enable I3C
Date: Sat, 9 Aug 2025 11:17:46 +0200 [thread overview]
Message-ID: <aJcSOlS1kfem0Bd2@shikoro> (raw)
In-Reply-To: <7737de72-701a-43ce-88a4-90d2d17c48f8@tuxon.dev>
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> - there is I3C_SET register (bit POC) which controls the I3C voltage, so, I
> presume, depending on the SW_I3C_VIO_SEL switch on the board (which
> selects the output of VDD_I3C regulator) the pins would have to be
> configured with proper power-source = <1800> or power-source = <1200>
I assumed the firmware is setting that bit. Never checked, though, and
can't do before end of August.
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next prev parent reply other threads:[~2025-08-09 9:17 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-07 15:14 [PATCH 0/4] arm64: dts: renesas: Enable I3C on RZ G3S/E Wolfram Sang
2025-08-07 15:14 ` [PATCH 1/4] arm64: dts: renesas: r9a08g045: Add I3C node Wolfram Sang
2025-08-09 5:05 ` Claudiu Beznea
2025-08-18 12:10 ` Geert Uytterhoeven
2025-08-07 15:14 ` [PATCH 2/4] arm64: dts: renesas: r9a09g047: " Wolfram Sang
2025-08-12 7:26 ` Geert Uytterhoeven
2025-08-18 12:24 ` Geert Uytterhoeven
2025-08-07 15:14 ` [PATCH 3/4] arm64: dts: renesas: rzg3s-smarc-som: Enable I3C Wolfram Sang
2025-08-09 5:09 ` Claudiu Beznea
2025-08-09 9:17 ` Wolfram Sang [this message]
2025-09-11 7:22 ` Wolfram Sang
2025-08-07 15:14 ` [PATCH 4/4] arm64: dts: renesas: rzg3e-smarc-som: " Wolfram Sang
2025-08-07 15:52 ` Biju Das
2025-08-07 17:00 ` wsa+renesas
2025-08-07 17:34 ` Biju Das
2025-08-08 14:55 ` kernel test robot
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