From: Mark Rutland <mark.rutland@arm.com>
To: Yicong Yang <yangyicong@huawei.com>
Cc: will@kernel.org, linux-arm-kernel@lists.infradead.org,
james.clark@linaro.org, robh@kernel.org,
anshuman.khandual@arm.com, jonathan.cameron@huawei.com,
hejunhao3@huawei.com, linuxarm@huawei.com,
prime.zeng@hisilicon.com, xuwei5@huawei.com,
wangyushan12@huawei.com, yangyicong@hisilicon.com
Subject: Re: [PATCH 1/2] perf: arm_pmuv3: Factor out PMCCNTR_EL0 use conditions
Date: Tue, 12 Aug 2025 11:25:07 +0100 [thread overview]
Message-ID: <aJsWg9g_Z9z-ejcL@J2N7QTR9R3> (raw)
In-Reply-To: <20250812080830.20796-2-yangyicong@huawei.com>
On Tue, Aug 12, 2025 at 04:08:29PM +0800, Yicong Yang wrote:
> From: Yicong Yang <yangyicong@hisilicon.com>
>
> PMCCNTR_EL0 is preferred for counting CPU_CYCLES under certain
> conditions. Factor out the condition check to a separate function
> for further extension. Add documents for better understanding.
> No functional changes intended.
>
> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
FWIW, splitting this oudt looks fine to me (with one nit below), so:
Acked-by: Mark Rutland <mark.rutland@arm.com>
> ---
> drivers/perf/arm_pmuv3.c | 30 ++++++++++++++++++++++++++++--
> 1 file changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c
> index f6d7bab5d555..95c899d07df5 100644
> --- a/drivers/perf/arm_pmuv3.c
> +++ b/drivers/perf/arm_pmuv3.c
> @@ -978,6 +978,33 @@ static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,
> return -EAGAIN;
> }
>
> +static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,
> + struct perf_event *event)
> +{
> + struct hw_perf_event *hwc = &event->hw;
> + unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
> +
> + /* PMCCNTR_EL0 can only be used for CPU_CYCLES event */
> + if (evtype != ARMV8_PMUV3_PERFCTR_CPU_CYCLES)
> + return false;
Nit: I don't think this comment is useful, and it could be deleted.
Mark.
> +
> + /*
> + * A CPU_CYCLES event with threshold counting cannot use PMCCNTR_EL0
> + * since it lacks threshold support.
> + */
> + if (armv8pmu_event_get_threshold(&event->attr))
> + return false;
> +
> + /*
> + * PMCCNTR_EL0 is not affected by BRBE controls like BRBCR_ELx.FZP.
> + * So don't use it for branch events.
> + */
> + if (has_branch_stack(event))
> + return false;
> +
> + return true;
> +}
> +
> static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
> struct perf_event *event)
> {
> @@ -986,8 +1013,7 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
> unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
>
> /* Always prefer to place a cycle counter into the cycle counter. */
> - if ((evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) &&
> - !armv8pmu_event_get_threshold(&event->attr) && !has_branch_stack(event)) {
> + if (armv8pmu_can_use_pmccntr(cpuc, event)) {
> if (!test_and_set_bit(ARMV8_PMU_CYCLE_IDX, cpuc->used_mask))
> return ARMV8_PMU_CYCLE_IDX;
> else if (armv8pmu_event_is_64bit(event) &&
> --
> 2.24.0
>
next prev parent reply other threads:[~2025-08-12 16:19 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-12 8:08 [PATCH 0/2] perf: arm_pmuv3: Don't use PMCCNTR_EL0 on SMT cores Yicong Yang
2025-08-12 8:08 ` [PATCH 1/2] perf: arm_pmuv3: Factor out PMCCNTR_EL0 use conditions Yicong Yang
2025-08-12 10:02 ` James Clark
2025-08-12 10:25 ` Mark Rutland [this message]
2025-08-12 8:08 ` [PATCH 2/2] perf: arm_pmuv3: Don't use PMCCNTR_EL0 on SMT cores Yicong Yang
2025-08-12 10:00 ` James Clark
2025-08-12 10:14 ` Yicong Yang
2025-08-12 10:22 ` Mark Rutland
2025-08-13 8:17 ` Yicong Yang
2025-08-12 10:31 ` James Clark
2025-08-13 8:32 ` Yicong Yang
2025-08-12 10:33 ` Mark Rutland
2025-08-13 8:03 ` Yicong Yang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aJsWg9g_Z9z-ejcL@J2N7QTR9R3 \
--to=mark.rutland@arm.com \
--cc=anshuman.khandual@arm.com \
--cc=hejunhao3@huawei.com \
--cc=james.clark@linaro.org \
--cc=jonathan.cameron@huawei.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linuxarm@huawei.com \
--cc=prime.zeng@hisilicon.com \
--cc=robh@kernel.org \
--cc=wangyushan12@huawei.com \
--cc=will@kernel.org \
--cc=xuwei5@huawei.com \
--cc=yangyicong@hisilicon.com \
--cc=yangyicong@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.