Re: [PATCH 3/7] pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info

[Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>]

Hi Biju,
Thank you for your patch.


On Thu, Aug 14, 2025 at 07:41:07PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> RZ/G3E GPT IP has prescale factor power of 2 where as that of RZ/G2L is 4.
> Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info for
> handling this difference.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Thanks & Regards,
Tommaso

> ---
>  drivers/pwm/pwm-rzg2l-gpt.c | 17 ++++++++++++-----
>  1 file changed, 12 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
> index bf989defa527..74bb0cca4ab4 100644
> --- a/drivers/pwm/pwm-rzg2l-gpt.c
> +++ b/drivers/pwm/pwm-rzg2l-gpt.c
> @@ -91,6 +91,7 @@
>  
>  struct rzg2l_gpt_info {
>  	u32 gtcr_tpcs_mask;
> +	u8 prescale_pow_of_two_mult_factor;
>  };
>  
>  struct rzg2l_gpt_chip {
> @@ -226,6 +227,7 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *rzg2l_gpt,
>  static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,
>  					      u32 val, u8 prescale)
>  {
> +	const struct rzg2l_gpt_info *info = rzg2l_gpt->info;
>  	u64 tmp;
>  
>  	/*
> @@ -235,15 +237,18 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,
>  	 *     < 2^32 * 2^10 * 2^20
>  	 *     = 2^62
>  	 */
> -	tmp = (u64)val << (2 * prescale);
> +	tmp = (u64)val << (info->prescale_pow_of_two_mult_factor * prescale);
>  	tmp *= USEC_PER_SEC;
>  
>  	return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz);
>  }
>  
> -static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale)
> +static u32 rzg2l_gpt_calculate_pv_or_dc(const struct rzg2l_gpt_info *info,
> +					u64 period_or_duty_cycle, u8 prescale)
>  {
> -	return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * prescale)),
> +	return min_t(u64,
> +		     DIV_ROUND_DOWN_ULL(period_or_duty_cycle,
> +					1 << (info->prescale_pow_of_two_mult_factor * prescale)),
>  		     U32_MAX);
>  }
>  
> @@ -254,6 +259,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,
>  
>  {
>  	struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
> +	const struct rzg2l_gpt_info *info = rzg2l_gpt->info;
>  	struct rzg2l_gpt_waveform *wfhw = _wfhw;
>  	u8 ch = RZG2L_GET_CH(pwm->hwpwm);
>  	u64 period_ticks, duty_ticks;
> @@ -287,12 +293,12 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,
>  	}
>  
>  	wfhw->prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);
> -	pv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale);
> +	pv = rzg2l_gpt_calculate_pv_or_dc(info, period_ticks, wfhw->prescale);
>  	wfhw->gtpr = pv;
>  	duty_ticks = mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_khz, USEC_PER_SEC);
>  	if (duty_ticks > period_ticks)
>  		duty_ticks = period_ticks;
> -	dc = rzg2l_gpt_calculate_pv_or_dc(duty_ticks, wfhw->prescale);
> +	dc = rzg2l_gpt_calculate_pv_or_dc(info, duty_ticks, wfhw->prescale);
>  	wfhw->gtccr = dc;
>  
>  	/*
> @@ -477,6 +483,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
>  
>  static const struct rzg2l_gpt_info rzg2l_data = {
>  	.gtcr_tpcs_mask = GENMASK(26, 24),
> +	.prescale_pow_of_two_mult_factor = 2,
>  };
>  
>  static const struct of_device_id rzg2l_gpt_of_table[] = {
> -- 
> 2.43.0
>