From: Sean Christopherson <seanjc@google.com>
To: "Maciej S. Szmigiero" <mail@maciej.szmigiero.name>
Cc: Naveen N Rao <naveen@kernel.org>,
mlevitsk@redhat.com, Paolo Bonzini <pbonzini@redhat.com>,
kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
Vasant Hegde <vasant.hegde@amd.com>,
Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Subject: Re: [EARLY RFC] KVM: SVM: Enable AVIC by default from Zen 4
Date: Tue, 19 Aug 2025 16:54:29 -0700 [thread overview]
Message-ID: <aKUOtQvIAN5FC0MC@google.com> (raw)
In-Reply-To: <7cfe68c2-a84a-4416-a9ca-3bf5225190a1@maciej.szmigiero.name>
On Tue, Aug 19, 2025, Maciej S. Szmigiero wrote:
> On 18.07.2025 10:19, Naveen N Rao wrote:
> As you can see, currently AVIC works there even without force_avic=1 so why
> now hide it behind that parameter if errata #1235 is supposedly not present
> on Zen3?
Yeah, I'm aligned with keeping the current semantics for force_avic (and by
extension for avic), and I'm pretty sure Naveen is as well.
> Also, this platform is apparently confident enough that the AVIC silicon is
> working correctly there to expose it in CPUID - maybe because that's CPU
> stepping 2 instead of the initial 0?
My vote is still to only enable AVIC by default for Zen4+. The story for Zen3
and earlier is just too messy.
prev parent reply other threads:[~2025-08-19 23:54 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-26 14:51 [EARLY RFC] KVM: SVM: Enable AVIC by default from Zen 4 Naveen N Rao (AMD)
2025-06-26 17:34 ` mlevitsk
2025-06-26 18:44 ` Sean Christopherson
2025-06-26 19:14 ` mlevitsk
2025-06-26 20:43 ` Jim Mattson
2025-06-27 8:25 ` Naveen N Rao
2025-07-07 23:21 ` Sean Christopherson
2025-07-18 8:19 ` Naveen N Rao
2025-08-19 13:34 ` Maciej S. Szmigiero
2025-08-19 23:54 ` Sean Christopherson [this message]
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