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Wed, 20 Aug 2025 01:46:33 -0700 (PDT) Date: Wed, 20 Aug 2025 10:46:31 +0200 From: Stephan Gerhold To: Mukesh Ojha Cc: Bjorn Andersson , Konrad Dybcio , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Mathieu Poirier , Abhinav Kumar , Bryan O'Donoghue , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, linux-remoteproc@vger.kernel.org Subject: Re: [PATCH v2 11/11] media: iris: Enable Secure PAS support with IOMMU managed by Linux Message-ID: References: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> <20250819165447.4149674-12-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250819165447.4149674-12-mukesh.ojha@oss.qualcomm.com> On Tue, Aug 19, 2025 at 10:24:46PM +0530, Mukesh Ojha wrote: > Most Qualcomm platforms feature a proprietary hypervisor (such as Gunyah > or QHEE), which typically handles IOMMU configuration. This includes > mapping memory regions and device memory resources for remote processors > by intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are > later removed during teardown. Additionally, SHM bridge setup is required > to enable memory protection for both remoteproc metadata and its memory > regions. > > When the hypervisor is absent, the operating system must perform these > configurations instead. > > Support for handling IOMMU and SHM setup in the absence of a hypervisor > is now in place. Extend the Iris driver to enable this functionality on > platforms where IOMMU is managed by Linux (i.e., non-Gunyah, non-QHEE). > > Additionally, the Iris driver must map the firmware and its required > resources to the firmware SID, which is now specified via the device tree. > > Co-developed-by: Vikash Garodia > Signed-off-by: Vikash Garodia > Signed-off-by: Mukesh Ojha > --- > drivers/media/platform/qcom/iris/iris_core.c | 9 +- > drivers/media/platform/qcom/iris/iris_core.h | 6 + > .../media/platform/qcom/iris/iris_firmware.c | 156 ++++++++++++++++-- > .../media/platform/qcom/iris/iris_firmware.h | 2 + > 4 files changed, 155 insertions(+), 18 deletions(-) > > [...] > diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/media/platform/qcom/iris/iris_firmware.c > index f1b5cd56db32..e3f2fe5c9d7a 100644 > --- a/drivers/media/platform/qcom/iris/iris_firmware.c > +++ b/drivers/media/platform/qcom/iris/iris_firmware.c > @@ -3,10 +3,18 @@ > * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. > */ > > +#include > #include > -#include > +#include > +#include > +#include > +#include > #include > #include > +#include > +#include > +#include > +#include > #include > > #include "iris_core.h" > @@ -17,15 +25,14 @@ > static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) > { > u32 pas_id = core->iris_platform_data->pas_id; > + struct qcom_scm_pas_ctx *ctx; > const struct firmware *firmware = NULL; > struct device *dev = core->dev; > - struct reserved_mem *rmem; > - struct device_node *node; > - phys_addr_t mem_phys; > - size_t res_size; > - ssize_t fw_size; > - void *mem_virt; > - int ret; > + struct reserved_mem *rmem = NULL; > + struct device_node *node = NULL; > + ssize_t fw_size = 0; > + void *mem_virt = NULL; > + int ret = 0; > > if (strlen(fw_name) >= MAX_FIRMWARE_NAME_SIZE - 4) > return -EINVAL; > @@ -39,36 +46,64 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) > if (!rmem) > return -EINVAL; > > - mem_phys = rmem->base; > - res_size = rmem->size; > + if (core->has_iommu) > + dev = core->fw.dev; > > + ctx = qcom_scm_pas_ctx_init(dev, pas_id, rmem->base, rmem->size, false); > + if (!ctx) > + return -ENOMEM; > + > + ctx->has_iommu = core->has_iommu; > ret = request_firmware(&firmware, fw_name, dev); > if (ret) > return ret; > > fw_size = qcom_mdt_get_size(firmware); > - if (fw_size < 0 || res_size < (size_t)fw_size) { > + if (fw_size < 0 || rmem->size < (size_t)fw_size) { > ret = -EINVAL; > goto err_release_fw; > } > > - mem_virt = memremap(mem_phys, res_size, MEMREMAP_WC); > + mem_virt = memremap(rmem->base, rmem->size, MEMREMAP_WC); > if (!mem_virt) { > ret = -ENOMEM; > goto err_release_fw; > } > > - ret = qcom_mdt_load(dev, firmware, fw_name, > - pas_id, mem_virt, mem_phys, res_size, NULL); > + ret = qcom_mdt_pas_load(ctx, firmware, fw_name, mem_virt, NULL); > if (ret) > goto err_mem_unmap; > > - ret = qcom_scm_pas_auth_and_reset(pas_id); > + if (core->has_iommu) { > + ret = iommu_map(core->fw.iommu_domain, 0, rmem->base, rmem->size, > + IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); What is the use case for IOMMU_PRIV here? You don't have this flag for the qcom_q6v5_pas change. > + if (ret) > + goto err_mem_unmap; > + > + /* > + * Firmware has no support for resource table for now, so, lets > + * pass NULL and zero for input resource table and input resource > + * table respectively. > + */ > + ret = qcom_mdt_pas_map_devmem_rscs(ctx, core->fw.iommu_domain, NULL, 0); > + if (ret) > + goto err_unmap_carveout; > + } > + > + ret = qcom_scm_pas_prepare_and_auth_reset(ctx); > if (ret) > - goto err_mem_unmap; > + goto err_unmap_devmem_rscs; > + > + core->fw.ctx = ctx; > > return ret; > > +err_unmap_devmem_rscs: > + if (core->has_iommu) > + qcom_mdt_pas_unmap_devmem_rscs(ctx, core->fw.iommu_domain); > +err_unmap_carveout: > + if (core->has_iommu) > + iommu_unmap(core->fw.iommu_domain, 0, rmem->size); > err_mem_unmap: > memunmap(mem_virt); > err_release_fw: > @@ -109,10 +144,97 @@ int iris_fw_load(struct iris_core *core) > > int iris_fw_unload(struct iris_core *core) > { > - return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); > + struct qcom_scm_pas_ctx *ctx; > + int ret; > + > + ctx = core->fw.ctx; > + ret = qcom_scm_pas_shutdown(ctx->peripheral); > + if (core->has_iommu) { > + iommu_unmap(core->fw.iommu_domain, 0, ctx->mem_size); > + qcom_mdt_pas_unmap_devmem_rscs(ctx, core->fw.iommu_domain); > + } > + > + return ret; > } > > int iris_set_hw_state(struct iris_core *core, bool resume) > { > return qcom_scm_set_remote_state(resume, 0); > } > + > +int iris_fw_init(struct iris_core *core) > +{ > + struct platform_device_info info; > + struct iommu_domain *iommu_dom; > + struct platform_device *pdev; > + struct device_node *np; > + int ret; > + > + np = of_get_child_by_name(core->dev->of_node, "video-firmware"); > + if (!np) > + return 0; You need a dt-bindings change for this as well. This is documented only for Venus. Thanks, Stephan