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From: Mostafa Saleh <smostafa@google.com>
To: Tao Tang <tangtao1634@phytium.com.cn>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
	"Eric Auger" <eric.auger@redhat.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Chen Baozi" <chenbaozi@phytium.com.cn>,
	jean-philippe@linaro.org,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Pierrick Bouvier" <pierrick.bouvier@linaro.org>
Subject: Re: [RFC 06/11] hw/arm/smmuv3: Plumb security state through core functions
Date: Sat, 23 Aug 2025 10:43:32 +0000	[thread overview]
Message-ID: <aKmbVIGWry9nH8j8@google.com> (raw)
In-Reply-To: <7b8acb9a-e3fe-461b-8495-42c7501a6a80@phytium.com.cn>

On Thu, Aug 21, 2025 at 12:25:40AM +0800, Tao Tang wrote:
> 
> On 2025/8/19 05:28, Mostafa Saleh wrote:
> > On Wed, Aug 06, 2025 at 11:11:29PM +0800, Tao Tang wrote:
> > > To support parallel processing of secure and non-secure streams, the
> > > SMMUv3 model needs to differentiate between the two contexts throughout
> > > its core logic. This commit is the foundational step to make the code
> > > security-state aware.
> > > 
> > > An is_secure flag, which will be used in subsequent patches to represent
> > > the transaction's security state, is now plumbed through the main
> > > processing paths.
> > > 
> > > This change is purely preparatory and introduces no functional changes
> > > for the existing non-secure path. All current call sites are updated
> > > to pass is_secure = false.
> > > 
> > > This refactoring paves the way for upcoming patches that will introduce
> > > separate TLB entries for secure transactions and enable a fully
> > > parallel secure/non-secure SMMU model.
> > > 
> > I think it’s easier to review if this patch was split (STE parsing,
> > page table handling and translation, TLB invalidation)
> > Also based on my comment on patch 2, stage-2 handling doesn’t seem correct to me.
> > 
> > Thanks,
> > Mostafa
> > 
> Hi Mostafa,
> 
> Thank you your suggestion.
> 
> You've made a very good point. This patch is indeed too large and tries to
> cover too many different areas. For the v2 series, I will break this patch
> down into logical parts as you suggested (STE parsing, page table handling,
> etc.).
> 
> I also acknowledge your concern about the stage-2 handling logic from your
> comment on patch 2. I have sent a separate, detailed reply to your feedback
> on patch #2 that outlines my new understanding.
> 
> And as you commented on patch #01:
> 
> > > Inside this TCG VM, a KVM guest was launched, and the same NVMe device was
> > > re-assigned to it via VFIO.
> > > Command line of KVM VM inside TCG VM is below:
> > > 
> > > sudo qemu-system-aarch64  \
> > > -enable-kvm  -m 1024  -cpu host  -M virt \
> > > -machine virt,gic-version=3 \
> > > -cpu max -append "nokaslr" -smp 1 \
> > > -monitor stdio \
> > > -kernel 5.15.Image \
> > > -initrd rootfs.cpio.gz \
> > > -display vnc=:22,id=primary \
> > > -device vfio-pci,host=00:01.0
> > > 
> > > The KVM guest was able to perform I/O on the device
> > > correctly, confirming that the non-secure path is not broken.
> > I gave the patches a quick test and they seem to have broken my
> > nested setup, I will look more into it and let you know what I find.
> > 
> > Thanks,
> > Mostafa
> > 
> I'm sorry to hear that it has broken your environment. Please don't hesitate
> to share any details, logs, or reproduction steps when you find them. I am
> more than happy to help reproduce the issue on my end to get it fixed as
> quickly as possible.
> 
> 
> I would be delighted to hear back from you on any of the topics we've
> discussed, as any further guidance you can offer would be invaluable.
> 

So far, I couldn’t repro, I remember getting permission errors, I will
keep the patches in my stack, and will let you know if I hit that again.

Thanks,
Mostafa

> Thanks,
> 
> Tao
> 
> 
> 


  reply	other threads:[~2025-08-23 10:43 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-06 15:11 [RFC 00/11] hw/arm/smmuv3: Add initial support for Secure State Tao Tang
2025-08-06 15:11 ` [RFC 01/11] hw/arm/smmuv3: Introduce secure registers and commands Tao Tang
2025-08-11 10:22   ` Philippe Mathieu-Daudé
2025-08-11 10:43     ` Philippe Mathieu-Daudé
2025-08-18 21:21   ` Mostafa Saleh
2025-08-06 15:11 ` [RFC 02/11] hw/arm/smmuv3: Implement read/write logic for secure registers Tao Tang
2025-08-06 21:53   ` Pierrick Bouvier
2025-08-10 16:54     ` Tao Tang
2025-08-12 17:12       ` Pierrick Bouvier
2025-08-18 21:24   ` Mostafa Saleh
2025-08-20 15:21     ` Tao Tang
2025-08-23 10:41       ` Mostafa Saleh
2025-09-11 15:27         ` Tao Tang
2025-09-15  9:14           ` Mostafa Saleh
2025-09-15  9:34             ` Eric Auger
2025-08-06 15:11 ` [RFC 03/11] hw/arm/smmuv3: Implement S_INIT for secure initialization Tao Tang
2025-08-18 21:26   ` Mostafa Saleh
2025-08-20 16:01     ` Tao Tang
2025-08-06 15:11 ` [RFC 04/11] hw/arm/smmuv3: Enable command processing for the Secure state Tao Tang
2025-08-06 21:55   ` Pierrick Bouvier
2025-08-10 16:59     ` Tao Tang
2025-08-11 10:34       ` Philippe Mathieu-Daudé
2025-08-12 17:27         ` Pierrick Bouvier
2025-08-12 17:39           ` Philippe Mathieu-Daudé
2025-08-12 18:42         ` Peter Maydell
2025-08-15  6:02           ` Tao Tang
2025-08-15 14:53             ` Peter Maydell
2025-08-17  3:46               ` Tao Tang
2025-08-06 15:11 ` [RFC 05/11] hw/arm/smmuv3: Support secure event queue and error handling Tao Tang
2025-08-11 10:41   ` Philippe Mathieu-Daudé
2025-08-06 15:11 ` [RFC 06/11] hw/arm/smmuv3: Plumb security state through core functions Tao Tang
2025-08-18 21:28   ` Mostafa Saleh
2025-08-20 16:25     ` Tao Tang
2025-08-23 10:43       ` Mostafa Saleh [this message]
2025-08-06 15:11 ` [RFC 07/11] hw/arm/smmuv3: Add separate address space for secure SMMU accesses Tao Tang
2025-08-06 15:11 ` [RFC 08/11] hw/arm/smmuv3: Enable secure-side stage 2 TLB invalidations Tao Tang
2025-08-06 15:11 ` [RFC 09/11] hw/arm/smmuv3: Make the configuration cache security-state aware Tao Tang
2025-08-06 15:11 ` [RFC 10/11] hw/arm/smmuv3: Differentiate secure TLB entries via keying Tao Tang
2025-08-06 21:11 ` [RFC 00/11] hw/arm/smmuv3: Add initial support for Secure State Pierrick Bouvier
2025-08-06 21:28 ` Pierrick Bouvier
2025-08-10 16:11   ` Tao Tang
2025-08-11 10:26     ` Philippe Mathieu-Daudé
2025-08-12 17:50       ` Pierrick Bouvier
2025-08-12 18:04     ` Pierrick Bouvier
2025-08-15  5:49       ` Tao Tang
2025-09-30  4:04         ` Tao Tang
2025-08-18 21:52 ` Mostafa Saleh

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