Re: [PATCH v2 00/14] hw/arm: add Beckhoff CX7200 board

["Edgar E. Iglesias" <edgar.iglesias@gmail.com>]

On Tue, Aug 19, 2025 at 05:40:14PM +0100, Peter Maydell wrote:
> On Fri, 15 Aug 2025 at 19:06, Peter Maydell <peter.maydell@linaro.org> wrote:
> >
> > On Fri, 15 Aug 2025 at 10:01, Corvin Köhne <corvin.koehne@gmail.com> wrote:
> > >
> > > From: Corvin Köhne <c.koehne@beckhoff.com>
> > >
> > > Hi,
> > >
> > > Beckhoff has build a board, called CX7200, based on the Xilinx Zynq A9
> > > platform. This commit series adds the Beckhoff CX7200 as new board variant to
> > > QEMU.
> > >
> > > The emulation is able to successfully boot an CX7200 image. The image includes
> > > some self tests executed on every boot. Only the cache self test fails due to
> > > QEMU emulating the cache as always being coherent. The self tests include f.e.:
> > >
> > > * Network
> > > * Flash
> > > * CCAT DMA + EEPROM [1]
> > > * TwinCAT (Beckhoff's automation control software [2])
> > >
> > > [1] https://github.com/beckhoff/ccat
> > > [2] https://www.beckhoff.com/en-us/products/automation/
> > >
> > > YannickV (14):
> > >   hw/timer: Make frequency configurable
> > >   hw/timer: Make PERIPHCLK period configurable
> > >   hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff
> > >   hw/arm/zynq-devcfg: Prevent unintended unlock during initialization
> > >   hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in
> > >     user mode
> > >   hw/dma/zynq-devcfg: Simulate dummy PL reset
> > >   hw/dma/zynq-devcfg: Indicate power-up status of PL
> > >   hw/dma/zynq-devcfg: Fix register memory
> > >   hw/misc: Add dummy ZYNQ DDR controller
> > >   hw/misc/zynq_slcr: Add logic for DCI configuration
> > >   hw/misc: Add Beckhoff CCAT device
> > >   hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d
> > >   hw/arm: Add new machine based on xilinx-zynq-a9 for Beckhoff CX7200
> > >   docs/system/arm: Add support for Beckhoff CX7200
> >
> > This patchset is on my list to review. As an initial request,
> > for a new board could we have a test in tests/functional/
> > please?
> 
> I've also now reviewed the two initial generic-arm patches
> and the ones where you add new device models. I had a
> quick scan through the bug fix patches to the existing
> zynq devices but I'd appreciate it if the Xilinx folks
> could review those ones.
>

Thanks Peter,

I reviewed patches 3 - 8 and 10.

Patch 5 and 10 have some minor whitespace issues, perhaps we could fix
on commit...

f5badc6fe5 (HEAD) hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in user mode
3: ../check.sh

ERROR: trailing whitespace
#24: FILE: hw/dma/xlnx-zynq-devcfg.c:192:
+    $

total: 1 errors, 0 warnings, 8 lines checked


e8874ea66c (HEAD, beckhoff) hw/misc/zynq_slcr: Add logic for DCI configuration
7: ../check.sh

ERROR: trailing whitespace
#72: FILE: hw/misc/zynq_slcr.c:571:
+        if (!FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && $

total: 1 errors, 0 warnings, 61 lines checked

Cheers,
Edgar