From: "Ahmed S. Darwish" <darwi@linutronix.de>
To: Borislav Petkov <bp@alien8.de>
Cc: Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Andrew Cooper <andrew.cooper3@citrix.com>,
"H. Peter Anvin" <hpa@zytor.com>,
David Woodhouse <dwmw2@infradead.org>,
Sean Christopherson <seanjc@google.com>,
Peter Zijlstra <peterz@infradead.org>,
Sohil Mehta <sohil.mehta@intel.com>,
John Ogness <john.ogness@linutronix.de>,
x86@kernel.org, x86-cpuid@lists.linux.dev,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 06/34] x86/cpuid: Introduce <asm/cpuid/leaf_types.h>
Date: Mon, 25 Aug 2025 16:56:08 +0200 [thread overview]
Message-ID: <aKx5iFEXVGlzWETl@lx-t490> (raw)
In-Reply-To: <20250825141803.GUaKxwm1lAAugFJHVQ@fat_crate.local>
Hi Boris,
On Mon, 25 Aug 2025, Borislav Petkov wrote:
>
> On Fri, Aug 15, 2025 at 09:01:59AM +0200, Ahmed S. Darwish wrote:
> > +struct leaf_0x1_0 {
> > + // eax
> > + u32 stepping : 4, // Stepping ID
>
> All those bit names in all those leafs: are they taken from the official
> documentation?
>
Yes, I've built the 86-cpuid-db XML database from the official sources.
Intel:
Intel® 64 and IA-32 Architectures Software Developer's Manual
Intel® Architecture Instruction Set Extensions and Future Features
Intel® CPUID Enumeration and Architectural MSRs
Intel® X86-S External Architectural Specification
Intel® Key Locker Specification
Intel® Architecture Memory Encryption Technologies Specification
Intel® Trust Domain CPU Architectural Extensions
Intel® Architecture Specification: Intel® Trust Domain Extensions (TDX)
Intel® Flexible Return and Event Delivery (FRED) Specification
AMD:
AMD64 Architecture Programmer’s Manual, Volumes 1–5
Preliminary Processor Programming Reference (PPR) for AMD Family 19h
Model 11h, Revision B1 Processors
Open-Source Register Reference For AMD Family 17h Processors Models 00h-2Fh
Transmeta:
Processor Recognition, Transmeta Corporation (2002/05/07)
This is also listed under the 'References' section of the project:
https://gitlab.com/x86-cpuid.org/x86-cpuid-db
There are some bitfields contributed by Intel and AMD developers that are
not yet in the official documentation. In such cases, I trusted that
such info is posted from developers within Intel and/or AMD.
>
> > +/*
> > + * Leaf 0x5
> > + * MONITOR/MWAIT instructions enumeration
> ^^^^^^^^^^^
> Let's drop all those tautologies - it is absolutely clear that it is an
> enumeration so no need for it. Just keep the minimum text that is needed to
> describe the bit. People can always use that to find the official
> documentation of they need more info.
>
will do.
>
> > +/*
> > + * Leaf 0x18
> > + * Intel determenestic address translation (TLB) parameters
>
> + * Intel determenestic address translation (TLB) parameters
> Unknown word [determenestic] in comment.
> Suggestions: ['deterministic',...
>
> spellchecker please.
>
will do.
[ I have a spellcheck CI pipeline for the XML database, but somehow I
missed checking the leaf description field :( ]
Thanks!
--
Ahmed S. Darwish
Linutronix GmbH
next prev parent reply other threads:[~2025-08-25 14:56 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-15 7:01 [PATCH v4 00/34] x86: Introduce a centralized CPUID data model Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 01/34] x86/cpuid: Remove transitional <asm/cpuid.h> header Ahmed S. Darwish
2025-08-15 10:11 ` [tip: x86/urgent] " tip-bot2 for Ahmed S. Darwish
2025-08-15 15:22 ` tip-bot2 for Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 02/34] ASoC: Intel: avs: Include CPUID header at file scope Ahmed S. Darwish
2025-08-18 14:56 ` Borislav Petkov
2025-08-18 15:14 ` Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 03/34] treewide: Explicitly include the x86 CPUID headers Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 04/34] x86/cpu: <asm/processor.h>: Do not include the CPUID API header Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 05/34] x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIs Ahmed S. Darwish
2025-08-15 7:01 ` [PATCH v4 06/34] x86/cpuid: Introduce <asm/cpuid/leaf_types.h> Ahmed S. Darwish
2025-08-25 14:18 ` Borislav Petkov
2025-08-25 14:56 ` Ahmed S. Darwish [this message]
2025-08-15 7:02 ` [PATCH v4 07/34] x86/cpuid: Introduce a centralized CPUID data model Ahmed S. Darwish
2025-08-15 15:34 ` Sean Christopherson
2025-08-18 13:49 ` Ahmed S. Darwish
2025-08-18 18:44 ` Sean Christopherson
2025-08-18 19:54 ` Ahmed S. Darwish
2025-08-18 21:29 ` Sean Christopherson
2025-08-19 13:10 ` Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 08/34] x86/cpuid: Introduce a centralized CPUID parser Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 09/34] x86/cpu: Use parsed CPUID(0x0) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 10/34] x86/lib: Add CPUID(0x1) CPU family and model calculation Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 11/34] x86/cpu: Use parsed CPUID(0x1) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 12/34] x86/cpuid: Parse CPUID(0x80000000) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 13/34] x86/cpu: Use parsed CPUID(0x80000000) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 14/34] x86/cpuid: Introduce a CPUID leaf x86 vendor table Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 15/34] x86/cpuid: Introduce CPUID parser debugfs interface Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 16/34] x86/cpuid: Parse CPUID(0x2) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 17/34] x86/cpuid: Warn once on invalid CPUID(0x2) iteration count Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 18/34] x86/cpuid: Introduce parsed CPUID(0x2) API Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 19/34] x86/cpu: Use parsed CPUID(0x2) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 20/34] x86/cacheinfo: " Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 21/34] x86/cpuid: Remove direct CPUID(0x2) query API Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 22/34] x86/cpuid: Parse 'deterministic cache parameters' CPUID leaves Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 23/34] x86/cacheinfo: Pass a 'struct cpuinfo_x86' refrence to CPUID(0x4) code Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 24/34] x86/cacheinfo: Use parsed CPUID(0x4) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 25/34] x86/cacheinfo: Use parsed CPUID(0x8000001d) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 26/34] x86/cpuid: Parse CPUID(0x80000005) and CPUID(0x80000006) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 27/34] x86/cacheinfo: Use auto-generated data types Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 28/34] x86/cacheinfo: Use parsed CPUID(0x80000005) and CPUID(0x80000006) Ahmed S. Darwish
2025-08-15 15:25 ` Dave Hansen
2025-08-18 15:38 ` Ahmed S. Darwish
2025-08-18 15:52 ` David Woodhouse
2025-08-18 17:00 ` Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 29/34] x86/amd_nb: Trickle down 'struct cpuinfo_x86' reference Ahmed S. Darwish
2025-08-18 2:54 ` kernel test robot
2025-08-18 14:47 ` Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 30/34] x86/cpuid: Use parsed CPUID(0x80000006) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 31/34] x86/cpu: Rescan CPUID table after PSN disable Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 32/34] x86/cpu: Rescan CPUID table after unlocking full CPUID range Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 33/34] x86/cpuid: Parse CPUID(0x16) Ahmed S. Darwish
2025-08-15 7:02 ` [PATCH v4 34/34] x86/tsc: Use parsed CPUID(0x16) Ahmed S. Darwish
2025-08-16 9:59 ` [PATCH v4 00/34] x86: Introduce a centralized CPUID data model David Woodhouse
2025-08-18 16:37 ` Ahmed S. Darwish
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