From: dmukhin@xen.org
To: Mykola Kvach <xakep.amatop@gmail.com>
Cc: xen-devel@lists.xenproject.org, andrew.cooper3@citrix.com,
anthony.perard@vates.tech, jbeulich@suse.com, julien@xen.org,
michal.orzel@amd.com, roger.pau@citrix.com,
sstabellini@kernel.org, dmukhin@ford.com
Subject: Re: [PATCH v6 05/15] emul/ns16x50: implement SCR register
Date: Sun, 7 Sep 2025 20:37:24 -0700 [thread overview]
Message-ID: <aL5PdLqikrwOnP0s@kraken> (raw)
In-Reply-To: <CAGeoDV_YrSrKTYj5LitZQzdcO9-QBCqVmnqE63hGAendiqNxpw@mail.gmail.com>
On Sun, Sep 07, 2025 at 12:24:24AM +0300, Mykola Kvach wrote:
> Hi Denis,
>
> On Sat, Sep 6, 2025 at 2:27 AM <dmukhin@xen.org> wrote:
> >
> > From: Denis Mukhin <dmukhin@ford.com>
> >
> > Add SCR register emulation to the I/O port handler.
> > Firmware (e.g. OVMF) may use SCR during the guest OS boot.
> >
> > Signed-off-by: Denis Mukhin <dmukhin@ford.com>
> > ---
> > Changes since v5:
> > - moved earlier in the series to simplify I/O handler population in
> > the follow on patches
> > - Link to v5: https://lore.kernel.org/xen-devel/20250828235409.2835815-11-dmukhin@ford.com/
> > ---
> > xen/common/emul/vuart/ns16x50.c | 27 +++++++++++++++++++++++++++
> > 1 file changed, 27 insertions(+)
> >
> > diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
> > index 7f479a5be4a2..51ec85e57627 100644
> > --- a/xen/common/emul/vuart/ns16x50.c
> > +++ b/xen/common/emul/vuart/ns16x50.c
> > @@ -103,6 +103,20 @@ static int ns16x50_io_write8(
> >
> > if ( ns16x50_dlab_get(vdev) && (reg == UART_DLL || reg == UART_DLM) )
> > regs[NS16X50_REGS_NUM + reg] = val;
> > + else
> > + {
> > + switch ( reg )
> > + {
> > + /* NB: Firmware (e.g. OVMF) may rely on SCR presence. */
> > + case UART_SCR:
> > + regs[UART_SCR] = val;
> > + break;
> > +
> > + default:
> > + rc = -EINVAL;
>
> In the previous commit, when ns16x50_dlab_get() was zero and UART_DLL
> or UART_DLM was accessed, the function returned 0. With this commit,
> the behavior changes: now an -EINVAL error is returned for both DLL
> and DLM when ns16x50_dlab_get() is zero.
>
> Should this be fixed in the previous commit, or is this change
> intentional in this one? Note that for 16-bit accesses you already
> return an error when ns16x50_dlab_get() is zero, so the behavior is
> inconsistent for 8-bit accesses to DLL/DLM.
I agree, it makes sense to move the switch() block with default register
handling to the previous DLL/DLM commit; will update.
Thanks!
next prev parent reply other threads:[~2025-09-08 3:37 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-05 23:26 [PATCH v6 00/15] x86: introduce NS16550-compatible UART emulator dmukhin
2025-09-05 23:27 ` [PATCH v6 01/15] emul/vuart: introduce framework for UART emulators dmukhin
2025-09-06 2:02 ` Stefano Stabellini
2025-09-06 9:43 ` Mykola Kvach
2025-09-08 7:16 ` dmukhin
2025-09-08 8:29 ` Mykola Kvach
2025-09-08 8:43 ` Jan Beulich
2025-09-08 9:45 ` dmukhin
2025-09-05 23:27 ` [PATCH v6 02/15] xen/8250-uart: update definitions dmukhin
2025-09-06 2:02 ` Stefano Stabellini
2025-09-06 14:57 ` Mykola Kvach
2025-09-08 8:36 ` dmukhin
2025-09-05 23:27 ` [PATCH v6 03/15] emul/ns16x50: implement emulator stub dmukhin
2025-09-06 0:34 ` dmukhin
2025-09-06 2:03 ` Stefano Stabellini
2025-09-06 4:18 ` dmukhin
2025-09-06 20:37 ` Mykola Kvach
2025-09-08 8:32 ` dmukhin
2025-09-08 8:37 ` Mykola Kvach
2025-09-08 9:59 ` dmukhin
2025-09-05 23:27 ` [PATCH v6 04/15] emul/ns16x50: implement DLL/DLM registers dmukhin
2025-09-06 2:03 ` Stefano Stabellini
2025-09-06 21:12 ` Mykola Kvach
2025-09-08 6:41 ` dmukhin
2025-09-05 23:27 ` [PATCH v6 05/15] emul/ns16x50: implement SCR register dmukhin
2025-09-06 2:03 ` Stefano Stabellini
2025-09-06 21:24 ` Mykola Kvach
2025-09-08 3:37 ` dmukhin [this message]
2025-09-05 23:27 ` [PATCH v6 06/15] emul/ns16x50: implement IER/IIR registers dmukhin
2025-09-06 1:42 ` Stefano Stabellini
2025-09-08 2:37 ` dmukhin
2025-09-05 23:27 ` [PATCH v6 07/15] emul/ns16x50: implement LCR/LSR registers dmukhin
2025-09-06 2:04 ` Stefano Stabellini
2025-09-05 23:27 ` [PATCH v6 08/15] emul/ns16x50: implement MCR/MSR registers dmukhin
2025-09-06 1:42 ` Stefano Stabellini
2025-09-08 2:35 ` dmukhin
2025-09-05 23:27 ` [PATCH v6 09/15] emul/ns16x50: implement RBR register dmukhin
2025-09-06 2:04 ` Stefano Stabellini
2025-09-05 23:27 ` [PATCH v6 10/15] emul/ns16x50: implement THR register dmukhin
2025-09-06 1:59 ` Stefano Stabellini
2025-09-08 2:50 ` dmukhin
2025-09-08 3:15 ` dmukhin
2025-09-05 23:27 ` [PATCH v6 11/15] emul/ns16x50: implement FCR register (write-only) dmukhin
2025-09-06 2:04 ` Stefano Stabellini
2025-09-05 23:27 ` [PATCH v6 12/15] emul/ns16550: implement dump_state() hook dmukhin
2025-09-05 23:27 ` [PATCH v6 13/15] x86/domain: enable per-domain I/O port bitmaps dmukhin
2025-09-05 23:27 ` [PATCH v6 14/15] xen/domain: allocate d->irq_caps before arch-specific initialization dmukhin
2025-09-05 23:27 ` [PATCH v6 15/15] emul/ns16x50: implement IRQ emulation via vIOAPIC dmukhin
2025-09-06 0:33 ` [PATCH v6 00/15] x86: introduce NS16550-compatible UART emulator dmukhin
2025-09-06 2:01 ` Stefano Stabellini
2025-09-08 9:04 ` Mykola Kvach
2025-09-08 14:19 ` Oleksii Kurochko
2025-09-08 14:23 ` Oleksii Kurochko
2025-09-08 23:51 ` Stefano Stabellini
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