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From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: "Clément Léger" <clement.leger@bootlin.com>,
	"Andrew Lunn" <andrew@lunn.ch>,
	"Heiner Kallweit" <hkallweit1@gmail.com>,
	"Russell King" <linux@armlinux.org.uk>,
	"David S. Miller" <davem@davemloft.net>,
	"Eric Dumazet" <edumazet@google.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Paolo Abeni" <pabeni@redhat.com>,
	"Geert Uytterhoeven" <geert+renesas@glider.be>,
	linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	"Biju Das" <biju.das.jz@bp.renesas.com>,
	"Fabrizio Castro" <fabrizio.castro.jz@renesas.com>,
	"Lad Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	stable@kernel.org
Subject: Re: [PATCH net-next v2] net: pcs: rzn1-miic: Correct MODCTRL register offset
Date: Thu, 28 Aug 2025 12:25:29 +0200	[thread overview]
Message-ID: <aLAumWuFtJrSi7Mv@ninjato> (raw)
In-Reply-To: <20250820170913.2037049-1-prabhakar.mahadev-lad.rj@bp.renesas.com>

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On Wed, Aug 20, 2025 at 06:09:13PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Correct the Mode Control Register (MODCTRL) offset for RZ/N MIIC.
> According to the R-IN Engine and Ethernet Peripherals Manual (Rev.1.30)
> [0], Table 10.1 "Ethernet Accessory Register List", MODCTRL is at offset
> 0x8, not 0x20 as previously defined.
> 
> Offset 0x20 actually maps to the Port Trigger Control Register (PTCTRL),
> which controls PTP_MODE[3:0] and RGMII_CLKSEL[4]. Using this incorrect
> definition prevented the driver from configuring the SW_MODE[4:0] bits
> in MODCTRL, which control the internal connection of Ethernet ports. As
> a result, the MIIC could not be switched into the correct mode, leading
> to link setup failures and non-functional Ethernet ports on affected
> systems.
> 
> [0] https://www.renesas.com/en/document/mah/rzn1d-group-rzn1s-group-rzn1l-group-users-manual-r-engine-and-ethernet-peripherals?r=1054571
> 
> Fixes: 7dc54d3b8d91 ("net: pcs: add Renesas MII converter driver")
> Cc: stable@kernel.org
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

I had a look now. Because the bootloader of my N1D board already set up
MODCTRL correctly, this write to the wrong register went unnoticed. I
verified that the now correctly written value (depending on DT config)
matches the value previously set by the bootloader. As a result,
everything keeps working. We were lucky. Or unlucky. Depending how you
look at it.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for this fix!


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  parent reply	other threads:[~2025-08-28 10:25 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-20 17:09 [PATCH net-next v2] net: pcs: rzn1-miic: Correct MODCTRL register offset Prabhakar
2025-08-20 17:46 ` Russell King (Oracle)
2025-08-21  6:51 ` Wolfram Sang
2025-08-21  7:12 ` Geert Uytterhoeven
2025-08-22  0:22 ` Jakub Kicinski
2025-08-22  7:56   ` Lad, Prabhakar
2025-08-28 10:25 ` Wolfram Sang [this message]
2025-08-28 10:30   ` Lad, Prabhakar

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