Re: [PATCH v4 2/2] drm/xe/xe2hpg: Add Wa_18041344222 for Xe2_HPG

[Harish Chegondi <harish.chegondi@intel.com>]

On Wed, Aug 27, 2025 at 03:11:35PM -0500, Lucas De Marchi wrote:
> On Wed, Aug 27, 2025 at 11:09:35AM -0700, Harish Chegondi wrote:
> > Add Wa_18041344222 for Xe2_HPG that requires disabling
> > the perf mode for subslice count for eustall sampling
> > when the enabled slices are discontiguous.
> > 
> > v4: Rebase
> 
> this changelog is not very useful, is it?
I wanted to let the reviewer know that v4 is just a rebase and no
other changes made. Should I remove the changelog or add more details ?
> 
> > v3: Skip the workaround for SRIOV VF
> > v2: Add Bspec references (Matt A)
> >    Rebase
> > 
> > Bspec: 79483, 56024
> > Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> > Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> > ---
> > drivers/gpu/drm/xe/regs/xe_gt_regs.h |  1 +
> > drivers/gpu/drm/xe/xe_gt_topology.c  | 17 +++++++++++++++++
> > drivers/gpu/drm/xe/xe_gt_topology.h  |  1 +
> > drivers/gpu/drm/xe/xe_rtp.c          |  6 ++++++
> > drivers/gpu/drm/xe/xe_rtp.h          |  2 ++
> > drivers/gpu/drm/xe/xe_wa.c           |  7 +++++++
> > 6 files changed, 34 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > index f96b2e2b3064..06cb6b02ec64 100644
> > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > @@ -522,6 +522,7 @@
> > 
> > #define TDL_CHICKEN				XE_REG_MCR(0xe5f4, XE_REG_OPTION_MASKED)
> > #define   QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE	REG_BIT(12)
> > +#define   EUSTALL_PERF_SAMPLING_DISABLE		REG_BIT(5)
> > 
> > #define LSC_CHICKEN_BIT_0			XE_REG_MCR(0xe7c8)
> > #define   DISABLE_D8_D16_COASLESCE		REG_BIT(30)
> > diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
> > index a0baa560dd71..0ed7dc9044a5 100644
> > --- a/drivers/gpu/drm/xe/xe_gt_topology.c
> > +++ b/drivers/gpu/drm/xe/xe_gt_topology.c
> > @@ -12,6 +12,7 @@
> > #include "regs/xe_gt_regs.h"
> > #include "xe_assert.h"
> > #include "xe_gt.h"
> > +#include "xe_gt_mcr.h"
> > #include "xe_gt_printk.h"
> > #include "xe_mmio.h"
> > #include "xe_wa.h"
> > @@ -328,3 +329,19 @@ bool xe_gt_has_compute_dss(struct xe_gt *gt, unsigned int dss)
> > {
> > 	return test_bit(dss, gt->fuse_topo.c_dss_mask);
> > }
> > +
> > +bool xe_gt_has_discontiguous_dss_groups(const struct xe_gt *gt)
> > +{
> > +	unsigned int xecore;
> > +	int last_group = -1;
> > +	u16 group, instance;
> > +
> > +	for_each_dss_steering(xecore, gt, group, instance) {
> > +		if (last_group != group) {
> > +			if (group - last_group > 1)
> > +				return true;
> > +			last_group = group;
> > +		}
> > +	}
> > +	return false;
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_gt_topology.h b/drivers/gpu/drm/xe/xe_gt_topology.h
> > index c8140704ad4c..fd08b382e259 100644
> > --- a/drivers/gpu/drm/xe/xe_gt_topology.h
> > +++ b/drivers/gpu/drm/xe/xe_gt_topology.h
> > @@ -47,4 +47,5 @@ xe_gt_topology_has_dss_in_quadrant(struct xe_gt *gt, int quad);
> > bool xe_gt_has_geometry_dss(struct xe_gt *gt, unsigned int dss);
> > bool xe_gt_has_compute_dss(struct xe_gt *gt, unsigned int dss);
> > 
> > +bool xe_gt_has_discontiguous_dss_groups(const struct xe_gt *gt);
> 
> mind the newline
Will remove
> 
> > #endif /* _XE_GT_TOPOLOGY_H_ */
> > diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
> > index 47ea1521dc80..b5f430d59f80 100644
> > --- a/drivers/gpu/drm/xe/xe_rtp.c
> > +++ b/drivers/gpu/drm/xe/xe_rtp.c
> > @@ -370,3 +370,9 @@ bool xe_rtp_match_psmi_enabled(const struct xe_gt *gt,
> > {
> > 	return xe_configfs_get_psmi_enabled(to_pci_dev(gt_to_xe(gt)->drm.dev));
> > }
> > +
> > +bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
> > +						  const struct xe_hw_engine *hwe)
> > +{
> > +	return xe_gt_has_discontiguous_dss_groups(gt);
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
> > index 7951fefdbe04..d0adb29db7dd 100644
> > --- a/drivers/gpu/drm/xe/xe_rtp.h
> > +++ b/drivers/gpu/drm/xe/xe_rtp.h
> > @@ -480,4 +480,6 @@ bool xe_rtp_match_not_sriov_vf(const struct xe_gt *gt,
> > bool xe_rtp_match_psmi_enabled(const struct xe_gt *gt,
> > 			       const struct xe_hw_engine *hwe);
> > 
> > +bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
> > +						  const struct xe_hw_engine *hwe);
> 
> ditto
Will remove.


Thanks
Harish.

> 
> > #endif
> > diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> > index 52c7df4c3afd..1d4efaca110e 100644
> > --- a/drivers/gpu/drm/xe/xe_wa.c
> > +++ b/drivers/gpu/drm/xe/xe_wa.c
> > @@ -612,6 +612,13 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> > 		       FUNC(xe_rtp_match_first_render_or_compute)),
> > 	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
> > 	},
> > +	{ XE_RTP_NAME("18041344222"),
> > +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
> > +		       FUNC(xe_rtp_match_first_render_or_compute),
> > +		       FUNC(xe_rtp_match_not_sriov_vf),
> > +		       FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
> > +	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
> > +	},
> > 
> > 	/* Xe2_LPM */
> > 
> > -- 
> > 2.48.1
> >