From: "Daniel P. Berrangé" <berrange@redhat.com>
To: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
"cfu@mips.com" <cfu@mips.com>, "mst@redhat.com" <mst@redhat.com>,
"marcel.apfelbaum@gmail.com" <marcel.apfelbaum@gmail.com>,
"dbarboza@ventanamicro.com" <dbarboza@ventanamicro.com>,
"philmd@linaro.org" <philmd@linaro.org>
Subject: Re: [PATCH v7 04/14] target/riscv: Add MIPS P8700 CSRs
Date: Mon, 1 Sep 2025 11:41:33 +0100 [thread overview]
Message-ID: <aLV4XVR6baQpZRD_@redhat.com> (raw)
In-Reply-To: <20250901102850.1172983-5-djordje.todorovic@htecgroup.com>
On Mon, Sep 01, 2025 at 10:29:02AM +0000, Djordje Todorovic wrote:
> Define MIPS CSRs used for P8700 CPU.
>
> Signed-off-by: Chao-ying Fu <cfu@mips.com>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu.c | 3 +
> target/riscv/cpu.h | 3 +
> target/riscv/meson.build | 1 +
> target/riscv/mips_csr.c | 228 +++++++++++++++++++++++++++++++++++++++
> 4 files changed, 235 insertions(+)
> create mode 100644 target/riscv/mips_csr.c
> diff --git a/target/riscv/mips_csr.c b/target/riscv/mips_csr.c
> new file mode 100644
> index 0000000000..2fc10b8618
> --- /dev/null
> +++ b/target/riscv/mips_csr.c
> @@ -0,0 +1,228 @@
> +/*
> + * MIPS-specific CSRs.
> + *
> + * Copyright (c) 2025 MIPS
> + *
> + * SPDX-License-Identifier: LGPL-2.1-or-later
What is the reason for this choice ?
New files are expected to be GPL-2.0-or-later, with any divergence
from this explained in the commit message.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
This should not be present on newly authored files - only pre-existing
code which predated our use of SPDX tags, because it creates the possible
problem of inconsistent license details - which is what you have here.
This is saying GPL-2.0-or-later, while the SDPX tag says LGPL-2.1-or-later
These points apply to multiple patches in this series.
Please make sure to run 'checkpatch.pl' on patches before submissions,
as it would have reported these problems.
With regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o- https://fstop138.berrange.com :|
|: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
next prev parent reply other threads:[~2025-09-01 10:42 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-01 10:29 [PATCH v7 00/14] riscv: Add support for MIPS P8700 CPU Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 01/14] hw/intc: Allow gaps in hartids for aclint and aplic Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 02/14] target/riscv: Add cpu_set_exception_base Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 04/14] target/riscv: Add MIPS P8700 CSRs Djordje Todorovic
2025-09-01 10:41 ` Daniel P. Berrangé [this message]
2025-09-03 8:38 ` Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 03/14] target/riscv: Add MIPS P8700 CPU Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 05/14] target/riscv: Add mips.ccmov instruction Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 06/14] target/riscv: Add mips.pref instruction Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 07/14] target/riscv: Add Xmipslsp instructions Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 08/14] hw/misc: Add RISC-V CMGCR device implementation Djordje Todorovic
2025-09-01 10:48 ` Daniel P. Berrangé
2025-09-01 10:29 ` [PATCH v7 10/14] hw/riscv: Add support for RISCV CPS Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 11/14] hw/riscv: Add support for MIPS Boston-aia board mode Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 09/14] hw/misc: Add RISC-V CPC device implementation Djordje Todorovic
2025-09-01 10:49 ` Daniel P. Berrangé
2025-09-01 10:29 ` [PATCH v7 12/14] hw/pci: Allow explicit function numbers in pci Djordje Todorovic
2025-09-01 11:16 ` Philippe Mathieu-Daudé
2025-09-01 10:29 ` [PATCH v7 13/14] riscv/boston-aia: Add an e1000e NIC in slot 0 func 1 Djordje Todorovic
2025-09-01 10:29 ` [PATCH v7 14/14] test/functional: Add test for boston-aia board Djordje Todorovic
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aLV4XVR6baQpZRD_@redhat.com \
--to=berrange@redhat.com \
--cc=Djordje.Todorovic@htecgroup.com \
--cc=cfu@mips.com \
--cc=dbarboza@ventanamicro.com \
--cc=marcel.apfelbaum@gmail.com \
--cc=mst@redhat.com \
--cc=philmd@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.