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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5608acfd2ffsm2500187e87.107.2025.09.06.12.24.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Sep 2025 12:24:56 -0700 (PDT) Date: Sat, 6 Sep 2025 22:24:54 +0300 From: Dmitry Baryshkov To: Sebastian Reichel Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Frank Wang , Zhang Yubing , Andy Yan , Maud Spierings , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC 1/2] dt-bindings: phy: rockchip-usbdp: add improved ports scheme Message-ID: References: <20250904-rock5b-dp-alt-mode-v1-0-23df726b31ce@collabora.com> <20250904-rock5b-dp-alt-mode-v1-1-23df726b31ce@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250904-rock5b-dp-alt-mode-v1-1-23df726b31ce@collabora.com> X-Authority-Analysis: v=2.4 cv=eMETjGp1 c=1 sm=1 tr=0 ts=68bc8a8b cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=xqWC_Br6kY4A:10 a=kj9zAlcOel0A:10 a=yJojWOMRYYMA:10 a=JfrnYn6hAAAA:8 a=QX4gbG5DAAAA:8 a=OfM26ny4dbP1suOavW4A:9 a=CjuIK1q_8ugA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 a=1CNFftbPRP8L7MoqJWF3:22 a=AbAUZ8qAyYyZVLSsDulk:22 X-Proofpoint-GUID: dphwztBexD9Ssq---6Ey4kF-WA9fcZW6 X-Proofpoint-ORIG-GUID: dphwztBexD9Ssq---6Ey4kF-WA9fcZW6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAwMCBTYWx0ZWRfXztSOyB+90Vln PFkfg0iRZsKKPuSdCvYgqVxH0aQ2x5K8yfEq9AKgrEAZQ8C6Klb6SqgK4FVD2iI4oBDVkqhiuHs 0d4UilaJTgFByGi9WwBQ6NOhHtvwtYFpqz1J+gzkJ6BR5ymABJGwTXETXYsmVuDf9FIF5oSd+jp rkhk61UXrXlNlc+xUoAgDzgEpQEYzodP9T+ebgEHXI+8nQFoRIyklpicHH0ohjB1NuIx0W55aCp Tka6LF/Q6MZm9BIPTCtwGYfy88nIYwhAeJcSuR15JqUrNYPA6wGzAXJCRee2bZ3i70O92YpBGIB mxY6ieUivGDgAfmTtbPueNc/eX0Y3dHzkm53dq5SsePZV6ntFOO+YRoCmGMYrMgDXrevyauu1Ch Gu6BbOgf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-06_07,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 adultscore=0 bulkscore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060000 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250906_122500_480600_C3F56B9B X-CRM114-Status: GOOD ( 30.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Sep 04, 2025 at 08:26:02PM +0200, Sebastian Reichel wrote: > Currently the Rockchip USBDP PHY as a very simply port scheme: It just > offers a single port, which is supposed to point towards the connector. > Usually with 2 endpoints, one for the USB-C superspeed port and one for > the USB-C SBU port. > > This scheme is not good enough to properly handle DP AltMode, so add > a new scheme, which has separate ports for everything. This has been > modelled after the Qualcomm QMP USB4-USB3-DP PHY controller binding > with a slight difference that there is an additional port for the > USB-C SBU port as the Rockchip USB-DP PHY also contains the mux. > > Signed-off-by: Sebastian Reichel > --- > .../bindings/phy/phy-rockchip-usbdp.yaml | 23 ++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > index 8b7059d5b1826fdec5170cf78d6e27f2bd6766bb..f728acf057e4046a4d254ee687af3451f17bcd01 100644 > --- a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > @@ -114,6 +114,29 @@ properties: > A port node to link the PHY to a TypeC controller for the purpose of > handling orientation switching. > > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of the PHY for USB (or DP when configured into 4 lane > + mode), which should point to the superspeed port of a USB connector. What abourt USB+DP mode, where each one gets 2 lanes? > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: Incoming endpoint from the USB controller > + > + port@2: > + $ref: /schemas/graph.yaml#/properties/port > + description: Incoming endpoint from the DisplayPort controller > + > + port@3: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of the PHY for DP, which should either point to the > + SBU port of a USB-C connector or a DisplayPort connector input port. I would suggest describing this port as 'DisplayPort AUX signals to be connected to the SBU port of a USB-C connector (maybe through the additinal mux, switch or retimer)'. It should not be confused with the actual DisplayPort signals (as those go through the port@0). In the Qualcomm world we currently do not describe this link from the PHY to the gpio-mux or retimer, but I think we will have to do that soon. > + > required: > - compatible > - reg > > -- > 2.50.1 > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip -- With best wishes Dmitry From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E677CA1002 for ; Sat, 6 Sep 2025 19:28:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5608acfd2ffsm2500187e87.107.2025.09.06.12.24.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Sep 2025 12:24:56 -0700 (PDT) Date: Sat, 6 Sep 2025 22:24:54 +0300 From: Dmitry Baryshkov To: Sebastian Reichel Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Frank Wang , Zhang Yubing , Andy Yan , Maud Spierings , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC 1/2] dt-bindings: phy: rockchip-usbdp: add improved ports scheme Message-ID: References: <20250904-rock5b-dp-alt-mode-v1-0-23df726b31ce@collabora.com> <20250904-rock5b-dp-alt-mode-v1-1-23df726b31ce@collabora.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250904-rock5b-dp-alt-mode-v1-1-23df726b31ce@collabora.com> X-Proofpoint-ORIG-GUID: 5AWCLn3uZXuxufCEK9b5r7P49cPuYLil X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAyNyBTYWx0ZWRfX1EaKnQXnITb6 tw+I7nrVk5TlpYKwcsZfE/oXkfeu2eGoLfazUuMRFeOsypT7xIz5RZ/F6gR9ybaWqhRlcLlLsXJ Zgbbin7/Kp+Utu7NtQ/L6UVj5PfnM/Oe1f48IidrJhhhLV2nvp+ckOVbGyBjTiOHTiazH9wlI1A vitIkzrftCHU27272HJatZfJT7nKDSnhYUFOk8qKO9OrQX3YnzLsmS6+dvgNFG1RVlO3RMyA2Gg JfOIVmHh8FjFzLfsQl1P0VL7seB97VjR/b+DMawcI1/iIh9uJqNVomsQ/AftNU2tNVNfMImEdZC iJSq2rt6GukT4BKG29h/fZedfRPJvO9ZymXqpUxoSl0iQCegFIdiBCp6NMI5kX3zRQhNYaj77Q5 uhoPGIhM X-Authority-Analysis: v=2.4 cv=cYXSrmDM c=1 sm=1 tr=0 ts=68bc8a8b cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=xqWC_Br6kY4A:10 a=kj9zAlcOel0A:10 a=yJojWOMRYYMA:10 a=JfrnYn6hAAAA:8 a=QX4gbG5DAAAA:8 a=OfM26ny4dbP1suOavW4A:9 a=CjuIK1q_8ugA:10 a=iYH6xdkBrDN1Jqds4HTS:22 a=1CNFftbPRP8L7MoqJWF3:22 a=AbAUZ8qAyYyZVLSsDulk:22 X-Proofpoint-GUID: 5AWCLn3uZXuxufCEK9b5r7P49cPuYLil X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-06_07,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 impostorscore=0 clxscore=1015 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060027 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250906_122501_214320_95021DBD X-CRM114-Status: GOOD ( 29.24 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Thu, Sep 04, 2025 at 08:26:02PM +0200, Sebastian Reichel wrote: > Currently the Rockchip USBDP PHY as a very simply port scheme: It just > offers a single port, which is supposed to point towards the connector. > Usually with 2 endpoints, one for the USB-C superspeed port and one for > the USB-C SBU port. > > This scheme is not good enough to properly handle DP AltMode, so add > a new scheme, which has separate ports for everything. This has been > modelled after the Qualcomm QMP USB4-USB3-DP PHY controller binding > with a slight difference that there is an additional port for the > USB-C SBU port as the Rockchip USB-DP PHY also contains the mux. > > Signed-off-by: Sebastian Reichel > --- > .../bindings/phy/phy-rockchip-usbdp.yaml | 23 ++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > index 8b7059d5b1826fdec5170cf78d6e27f2bd6766bb..f728acf057e4046a4d254ee687af3451f17bcd01 100644 > --- a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > @@ -114,6 +114,29 @@ properties: > A port node to link the PHY to a TypeC controller for the purpose of > handling orientation switching. > > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of the PHY for USB (or DP when configured into 4 lane > + mode), which should point to the superspeed port of a USB connector. What abourt USB+DP mode, where each one gets 2 lanes? > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: Incoming endpoint from the USB controller > + > + port@2: > + $ref: /schemas/graph.yaml#/properties/port > + description: Incoming endpoint from the DisplayPort controller > + > + port@3: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of the PHY for DP, which should either point to the > + SBU port of a USB-C connector or a DisplayPort connector input port. I would suggest describing this port as 'DisplayPort AUX signals to be connected to the SBU port of a USB-C connector (maybe through the additinal mux, switch or retimer)'. It should not be confused with the actual DisplayPort signals (as those go through the port@0). In the Qualcomm world we currently do not describe this link from the PHY to the gpio-mux or retimer, but I think we will have to do that soon. > + > required: > - compatible > - reg > > -- > 2.50.1 > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip -- With best wishes Dmitry -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38483CA1012 for ; Sat, 6 Sep 2025 19:26:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; 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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5608acfd2ffsm2500187e87.107.2025.09.06.12.24.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Sep 2025 12:24:56 -0700 (PDT) Date: Sat, 6 Sep 2025 22:24:54 +0300 From: Dmitry Baryshkov To: Sebastian Reichel Cc: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Frank Wang , Zhang Yubing , Andy Yan , Maud Spierings , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC 1/2] dt-bindings: phy: rockchip-usbdp: add improved ports scheme Message-ID: References: <20250904-rock5b-dp-alt-mode-v1-0-23df726b31ce@collabora.com> <20250904-rock5b-dp-alt-mode-v1-1-23df726b31ce@collabora.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250904-rock5b-dp-alt-mode-v1-1-23df726b31ce@collabora.com> X-Authority-Analysis: v=2.4 cv=Yv8PR5YX c=1 sm=1 tr=0 ts=68bc8a8b cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=xqWC_Br6kY4A:10 a=kj9zAlcOel0A:10 a=yJojWOMRYYMA:10 a=JfrnYn6hAAAA:8 a=QX4gbG5DAAAA:8 a=OfM26ny4dbP1suOavW4A:9 a=CjuIK1q_8ugA:10 a=iYH6xdkBrDN1Jqds4HTS:22 a=1CNFftbPRP8L7MoqJWF3:22 a=AbAUZ8qAyYyZVLSsDulk:22 X-Proofpoint-GUID: tH5HRicY5VQDhQd5vW9HnMti5EoEOcn1 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAxOCBTYWx0ZWRfX71bbEfLHavSz mfrlgPcy9i+sJdsI9RdRNKLvJWe/puOxZo68TWLcFdGe1qJm7IC+yiIE1eOHZHAvdmGABYn2KgD +ejsZEMbe+x2Uu8de2hR7AAUvEpjfwtgRTawd8DVA4GZnArTnPeKnyIIEwXvJgEryedimFscDe2 ZeZzxrSDZhcNCJeHUWnRM9G29cH3l6aVHZpmtu3sWuhoow5QCY0lQaf9K4T9zkr8r+w11FsibNJ GCzhyNdd5bdF0GK0XJp0TRr7OyCxC1/H03gEBrkcBtQFAPRBpGbZ3CjmUnfdlkni5kQMx4PDhlB h4jjTb9dZVubdOycm517+EJpIjsHDS1QW01SiM39BeY0pxglNRH4MbtMY+sdTsOGHwTMXnuSiPe APC0bGQP X-Proofpoint-ORIG-GUID: tH5HRicY5VQDhQd5vW9HnMti5EoEOcn1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-06_07,2025-09-04_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 suspectscore=0 phishscore=0 clxscore=1015 spamscore=0 priorityscore=1501 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060018 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250906_122500_527560_C7BFA052 X-CRM114-Status: GOOD ( 29.89 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org On Thu, Sep 04, 2025 at 08:26:02PM +0200, Sebastian Reichel wrote: > Currently the Rockchip USBDP PHY as a very simply port scheme: It just > offers a single port, which is supposed to point towards the connector. > Usually with 2 endpoints, one for the USB-C superspeed port and one for > the USB-C SBU port. > > This scheme is not good enough to properly handle DP AltMode, so add > a new scheme, which has separate ports for everything. This has been > modelled after the Qualcomm QMP USB4-USB3-DP PHY controller binding > with a slight difference that there is an additional port for the > USB-C SBU port as the Rockchip USB-DP PHY also contains the mux. > > Signed-off-by: Sebastian Reichel > --- > .../bindings/phy/phy-rockchip-usbdp.yaml | 23 ++++++++++++++++++++++ > 1 file changed, 23 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > index 8b7059d5b1826fdec5170cf78d6e27f2bd6766bb..f728acf057e4046a4d254ee687af3451f17bcd01 100644 > --- a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml > @@ -114,6 +114,29 @@ properties: > A port node to link the PHY to a TypeC controller for the purpose of > handling orientation switching. > > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of the PHY for USB (or DP when configured into 4 lane > + mode), which should point to the superspeed port of a USB connector. What abourt USB+DP mode, where each one gets 2 lanes? > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: Incoming endpoint from the USB controller > + > + port@2: > + $ref: /schemas/graph.yaml#/properties/port > + description: Incoming endpoint from the DisplayPort controller > + > + port@3: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output endpoint of the PHY for DP, which should either point to the > + SBU port of a USB-C connector or a DisplayPort connector input port. I would suggest describing this port as 'DisplayPort AUX signals to be connected to the SBU port of a USB-C connector (maybe through the additinal mux, switch or retimer)'. It should not be confused with the actual DisplayPort signals (as those go through the port@0). In the Qualcomm world we currently do not describe this link from the PHY to the gpio-mux or retimer, but I think we will have to do that soon. > + > required: > - compatible > - reg > > -- > 2.50.1 > > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip -- With best wishes Dmitry _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip