Re: [PATCH v11 04/13] drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Thu, Aug 21, 2025 at 03:14:46PM +0100, Tvrtko Ursulin wrote:
> Emit MI_FLUSH_DW_CCS when invalidating on auxccs platforms.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_ring_ops.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index e7c23fd04011..752dea0a9234 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -275,15 +275,16 @@ static void __emit_job_gen12_xcs(struct xe_sched_job *job, struct xe_lrc *lrc,
>  			      class == XE_ENGINE_CLASS_VIDEO_DECODE ||
>  			      class == XE_ENGINE_CLASS_VIDEO_ENHANCE);
>  	const bool invalidate_tlb = aux_ccs || job->ring_ops_flush_tlb;
> +	const u32 flags = aux_ccs && class == XE_ENGINE_CLASS_COPY ?
> +			  MI_FLUSH_DW_CCS : 0;
>  
>  	i = emit_copy_timestamp(lrc, dw, i);
>  
>  	if (invalidate_tlb) {
>  		dw[i++] = preparser_disable(true);
>  		i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
> -					seqno,
> -					MI_INVALIDATE_TLB,
> -					dw, i);
> +					seqno, MI_INVALIDATE_TLB | flags, dw,
> +					i);
>  		/* hsdes: 1809175790 */
>  		if (aux_ccs) {
>  			struct xe_reg reg;
> -- 
> 2.48.0
>