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[34.142.178.23]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-26175efc667sm64942635ad.112.2025.09.15.04.10.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 04:10:50 -0700 (PDT) Date: Mon, 15 Sep 2025 11:10:43 +0000 From: Pranjal Shrivastava To: Marc Zyngier Cc: Will Deacon , Mostafa Saleh , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, robin.murphy@arm.com, jean-philippe@linaro.org, qperret@google.com, tabba@google.com, jgg@ziepe.ca, mark.rutland@arm.com Subject: Re: [PATCH v4 03/28] KVM: arm64: pkvm: Add pkvm_time_get() Message-ID: References: <20250819215156.2494305-1-smostafa@google.com> <20250819215156.2494305-4-smostafa@google.com> <86frcvd3hb.wl-maz@kernel.org> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <86frcvd3hb.wl-maz@kernel.org> On Tue, Sep 09, 2025 at 04:56:16PM +0100, Marc Zyngier wrote: > On Tue, 09 Sep 2025 15:16:26 +0100, > Will Deacon wrote: > > > > On Tue, Aug 19, 2025 at 09:51:31PM +0000, Mostafa Saleh wrote: > > > Add a function to return time in us. > > > > > > This can be used from IOMMU drivers while waiting for conditions as > > > for SMMUv3 TLB invalidation waiting for sync. > > > > > > Signed-off-by: Mostafa Saleh > > > Signed-off-by: Jean-Philippe Brucker > > > --- > > > arch/arm64/kvm/hyp/include/nvhe/pkvm.h | 2 ++ > > > arch/arm64/kvm/hyp/nvhe/setup.c | 4 ++++ > > > arch/arm64/kvm/hyp/nvhe/timer-sr.c | 33 ++++++++++++++++++++++++++ > > > 3 files changed, 39 insertions(+) > > [...] > > > > +#define SEC_TO_US 1000000 > > > + > > > +int pkvm_timer_init(void) > > > +{ > > > + timer_freq = read_sysreg(cntfrq_el0); > > > + /* > > > + * TODO: The highest privileged level is supposed to initialize this > > > + * register. But on some systems (which?), this information is only > > > + * contained in the device-tree, so we'll need to find it out some other > > > + * way. > > > + */ > > > + if (!timer_freq || timer_freq < SEC_TO_US) > > > + return -ENODEV; > > > + return 0; > > > +} > > > > Right, I think the frequency should be provided by the host once the arch > > timer driver has probed successfully. Relying on CNTFRQ isn't viable imo. > Are platforms are using DT to change this value? Because I think TF-A mandates [1] this value to be set, from the docs: BL31 programs the CNTFRQ_EL0 register with the clock frequency of the system counter, which is provided by the platform. Even the TF-A porting guide [2] mandates it to be set. > We can always patch the value in, à la kimage_voffset. But it really > begs the question: who is their right mind doesn't set CNTFRQ_EL0 to > something sensible? Why should we care about supporting such > contraption? > > I'd be happy to simply disable KVM when CNTFRQ_EL0 is misprogrammed, > or that the device tree provides a clock frequency. Because there is > no good way to support a guest in that case. > And even if someone choses not to use TF-A, IIUC, doesn't the aarch64 linux boot protocol[3] mandate CNTFRQ must be programmed with the timer frequency? As per the doc: Before jumping into the kernel, the following conditions must be met: [...] - Architected timers CNTFRQ must be programmed with the timer frequency and CNTVOFF must be programmed with a consistent value on all CPUs. Thanks, Praan [1] https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html [2] https://trustedfirmware-a.readthedocs.io/en/latest/porting-guide.html#function-plat-get-syscnt-freq2-mandatory [3] https://www.kernel.org/doc/Documentation/arm64/booting.txt